The attached patch corrects the definitions of the two FSMC ECC registers, and typo-fixes the definition of the ECC Enable bit. (You can perhaps guess what I've been working on today...)
Regards, Ross -- Embedded Software Engineer, eCosCentric Limited. Barnwell House, Barnwell Drive, Cambridge CB5 8UU, UK. Registered in England no. 4422071. www.ecoscentric.com
diff --git a/packages/hal/cortexm/stm32/var/current/ChangeLog b/packages/hal/cortexm/stm32/var/current/ChangeLog index e233a7d..c1ce7f9 100644 --- a/packages/hal/cortexm/stm32/var/current/ChangeLog +++ b/packages/hal/cortexm/stm32/var/current/ChangeLog @@ -1,3 +1,7 @@ +2009-10-26 Ross Younger <[email protected]> + + * include/var_io.h: Minor corrections to the FSMC register defs. + 2009-08-10 Simon Kallweit <[email protected]> * include/var_io.h: Added more register definitions for FSMC diff --git a/packages/hal/cortexm/stm32/var/current/include/var_io.h b/packages/hal/cortexm/stm32/var/current/include/var_io.h index e73102a..6c296f9 100644 --- a/packages/hal/cortexm/stm32/var/current/include/var_io.h +++ b/packages/hal/cortexm/stm32/var/current/include/var_io.h @@ -1585,10 +1585,14 @@ __externC void hal_stm32_bd_protect( int protect ); #define CYGHWR_HAL_STM32_FSMC_SR2 0x64 #define CYGHWR_HAL_STM32_FSMC_PMEM2 0x68 #define CYGHWR_HAL_STM32_FSMC_PATT2 0x6C +#define CYGHWR_HAL_STM32_FSMC_ECCR2 0x74 + #define CYGHWR_HAL_STM32_FSMC_PCR3 0x80 #define CYGHWR_HAL_STM32_FSMC_SR3 0x84 #define CYGHWR_HAL_STM32_FSMC_PMEM3 0x88 #define CYGHWR_HAL_STM32_FSMC_PATT3 0x8C +#define CYGHWR_HAL_STM32_FSMC_ECCR3 0x94 + #define CYGHWR_HAL_STM32_FSMC_PCR4 0xC0 #define CYGHWR_HAL_STM32_FSMC_SR4 0xC4 #define CYGHWR_HAL_STM32_FSMC_PMEM4 0xC8 @@ -1596,8 +1600,6 @@ __externC void hal_stm32_bd_protect( int protect ); #define CYGHWR_HAL_STM32_FSMC_PIO4 0xB0 -#define CYGHWR_HAL_STM32_FSMC_ECCR2 0x54 -#define CYGHWR_HAL_STM32_FSMC_ECCR3 0x74 #define CYGHWR_HAL_STM32_FSMC_BANK2_BASE 0x70000000 #define CYGHWR_HAL_STM32_FSMC_BANK3_BASE 0x80000000 @@ -1613,7 +1615,7 @@ __externC void hal_stm32_bd_protect( int protect ); #define CYGHWR_HAL_STM32_FSMC_PCR_PTYP_NAND BIT_(3) #define CYGHWR_HAL_STM32_FSMC_PCR_PWID_8 VALUE_(4,0) #define CYGHWR_HAL_STM32_FSMC_PCR_PWID_16 VALUE_(4,1) -#define CYGHWR_HAL_STM32_FSMC_PCR_EECEN BIT_(6) +#define CYGHWR_HAL_STM32_FSMC_PCR_ECCEN BIT_(6) #define CYGHWR_HAL_STM32_FSMC_PCR_ADLOW BIT_(8) #define CYGHWR_HAL_STM32_FSMC_PCR_TCLR(__x) VALUE_(9,__x) #define CYGHWR_HAL_STM32_FSMC_PCR_TAR(__x) VALUE_(13,__x)
