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--- Comment #12 from Ilija Kocho <ili...@siva.com.mk> --- (In reply to comment #7) > I assume from Ilija's comments that DMA bypasses the cache, hence the need > to invalidate it. > [snip] > I assume the TCD limitation is because the eDMA logic in the device is > connected tightly with the memory bus logic and can't route through the > cache, similar to how DMA works directly on memory without the cache. eDMA has no access to cache, but the problem could be (also) solved with cache synchronisation/invalidation. However, it would require extra CPU time and since TCD typically occupy little memory (even cumulative), for best performance I have chosen to put them in SRAM [by default]. Same discussion applies to Ethernet buffer descriptors. [snip] -- You are receiving this mail because: You are on the CC list for the bug.
