Revision: 14449
http://sourceforge.net/p/edk2/code/14449
Author: oliviermartin
Date: 2013-07-01 14:14:37 +0000 (Mon, 01 Jul 2013)
Log Message:
-----------
ArmPlatformPkg/ArmVExpressLibCTA15-A7: Mapped the extra 1GB of DRAM in the MMU
ARM Versatile Express TC2 Core Tile has two profiles: the 1GB DRAM core tile or
the 2GB DRAM core tile profiles.
By default UEFI assumes, it is the 1GB core tile. In case of 2GB DRAM it
declares
this additional 1GB resource system memory to UEFI. But the previous code did
not map this memory in the MMU Page Table.
So, the memory was allocatable by UEFI modules, but was not accessible by the
CPU
(because not mapped).
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <[email protected]>
Reviewed-by: Leif Lindholm <[email protected]>
Modified Paths:
--------------
trunk/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Mem.c
Modified:
trunk/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Mem.c
===================================================================
---
trunk/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Mem.c
2013-06-28 22:44:21 UTC (rev 14448)
+++
trunk/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Mem.c
2013-07-01 14:14:37 UTC (rev 14449)
@@ -59,20 +59,6 @@
CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
}
- // Detect if it is a 1GB or 2GB Test Chip
- // [16:19]: 0=1GB TC2, 1=2GB TC2
- if (MmioRead32(ARM_VE_SYS_PROCID0_REG) & (0xF << 16)) {
- DEBUG((EFI_D_ERROR,"Info: 2GB Test Chip 2 detected.\n"));
- BuildResourceDescriptorHob (
- EFI_RESOURCE_SYSTEM_MEMORY,
- EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_TESTED,
- PcdGet32 (PcdSystemMemoryBase) + PcdGet32 (PcdSystemMemorySize),
- 0x40000000
- );
- }
-
#ifdef ARM_BIGLITTLE_TC2
// Secure NOR0 Flash
VirtualMemoryTable[Index].PhysicalBase = ARM_VE_SEC_NOR0_BASE;
@@ -164,6 +150,26 @@
VirtualMemoryTable[Index].Length = PcdGet32 (PcdSystemMemorySize);
VirtualMemoryTable[Index].Attributes = CacheAttributes;
+ // Detect if it is a 1GB or 2GB Test Chip
+ // [16:19]: 0=1GB TC2, 1=2GB TC2
+ if (MmioRead32(ARM_VE_SYS_PROCID0_REG) & (0xF << 16)) {
+ DEBUG((EFI_D_ERROR,"Info: 2GB Test Chip 2 detected.\n"));
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED,
+ PcdGet32 (PcdSystemMemoryBase) + PcdGet32 (PcdSystemMemorySize),
+ SIZE_1GB
+ );
+
+ // Map the additional 1GB into the MMU
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdSystemMemoryBase)
+ PcdGet32 (PcdSystemMemorySize);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdSystemMemoryBase)
+ PcdGet32 (PcdSystemMemorySize);
+ VirtualMemoryTable[Index].Length = SIZE_1GB;
+ VirtualMemoryTable[Index].Attributes = CacheAttributes;
+ }
+
// End of Table
VirtualMemoryTable[++Index].PhysicalBase = 0;
VirtualMemoryTable[Index].VirtualBase = 0;
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