Revision: 14606
http://sourceforge.net/p/edk2/code/14606
Author: oliviermartin
Date: 2013-08-27 09:17:20 +0000 (Tue, 27 Aug 2013)
Log Message:
-----------
SCR_EL3 is the control register for setting the security state
modified the comment which can mislead.
The "ldr r0, [r1]" is overrided with a immediate "mov ro, #3"
instruction. This mov instruction will over write the contents
of the ro register. So replacing 'mov' by 'orr' instruction would
prevent to override the original value.
This patch assumes mov is the right instruction to be retained
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Girish K S <[email protected]>
Signed-off-by: Olivier Martin <[email protected]>
Revision Links:
--------------
http://sourceforge.net/p/edk2/code/0
http://sourceforge.net/p/edk2/code/1
Modified Paths:
--------------
trunk/edk2/ArmPlatformPkg/ArmVExpressPkg/Scripts/uefi-aarch64-bootstrap/boot.S
Modified:
trunk/edk2/ArmPlatformPkg/ArmVExpressPkg/Scripts/uefi-aarch64-bootstrap/boot.S
===================================================================
---
trunk/edk2/ArmPlatformPkg/ArmVExpressPkg/Scripts/uefi-aarch64-bootstrap/boot.S
2013-08-27 09:01:54 UTC (rev 14605)
+++
trunk/edk2/ArmPlatformPkg/ArmVExpressPkg/Scripts/uefi-aarch64-bootstrap/boot.S
2013-08-27 09:17:20 UTC (rev 14606)
@@ -57,7 +57,7 @@
b.ne start_ns // skip EL3 initialisation
mov x0, #0x30 // RES1
- orr x0, x0, #(1 << 0) // Non-secure EL1
+ orr x0, x0, #(1 << 0) // Non-secure bit
orr x0, x0, #(1 << 8) // HVC enable
orr x0, x0, #(1 << 10) // 64-bit EL2
msr scr_el3, x0
@@ -88,7 +88,7 @@
2: ldr x1, =GIC_CPU_BASE // GICC_CTLR
ldr w0, [x1]
- mov w0, #3 // EnableGrp0 | EnableGrp1
+ orr w0, w0, #3 // EnableGrp0 | EnableGrp1
str w0, [x1]
mov w0, #1 << 7 // allow NS access to GICC_PMR
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