Revision: 14762
http://sourceforge.net/p/edk2/code/14762
Author: vanjeff
Date: 2013-10-10 07:37:14 +0000 (Thu, 10 Oct 2013)
Log Message:
-----------
Sync patch r14760 from main trunk.
Just like EhciDxe, do not reset host controller when debug capability is
enabled in XhciDxe driver.
Revision Links:
--------------
http://sourceforge.net/p/edk2/code/14760
Modified Paths:
--------------
branches/UDK2010.SR1/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
branches/UDK2010.SR1/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h
branches/UDK2010.SR1/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
branches/UDK2010.SR1/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
Modified: branches/UDK2010.SR1/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
===================================================================
--- branches/UDK2010.SR1/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c 2013-10-10
05:57:50 UTC (rev 14761)
+++ branches/UDK2010.SR1/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c 2013-10-10
07:37:14 UTC (rev 14762)
@@ -164,9 +164,14 @@
// Flow through, same behavior as Host Controller Reset
//
case EFI_USB_HC_RESET_HOST_CONTROLLER:
- //
- // Host Controller must be Halt when Reset it
- //
+ if (((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset) & 0xFF) ==
XHC_CAP_USB_DEBUG) &&
+ ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) &
BIT0) != 0)) {
+ Status = EFI_SUCCESS;
+ goto ON_EXIT;
+ }
+ //
+ // Host Controller must be Halt when Reset it
+ //
if (!XhcIsHalt (Xhc)) {
Status = XhcHaltHC (Xhc, XHC_GENERIC_TIMEOUT);
@@ -1740,22 +1745,24 @@
//
PageSize = XhcReadOpReg(Xhc, XHC_PAGESIZE_OFFSET) & XHC_PAGESIZE_MASK;
Xhc->PageSize = 1 << (HighBitSet32(PageSize) + 12);
-
- ExtCapReg = (UINT16) (Xhc->HcCParams.Data.ExtCapReg);
- Xhc->ExtCapRegBase = ExtCapReg << 2;
- Xhc->UsbLegSupOffset = XhcGetLegSupCapAddr (Xhc);
-
- DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: Capability length 0x%x\n",
Xhc->CapLength));
- DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: HcSParams1 0x%x\n", Xhc->HcSParams1));
+
+ ExtCapReg = (UINT16) (Xhc->HcCParams.Data.ExtCapReg);
+ Xhc->ExtCapRegBase = ExtCapReg << 2;
+ Xhc->UsbLegSupOffset = XhcGetCapabilityAddr (Xhc, XHC_CAP_USB_LEGACY);
+ Xhc->DebugCapSupOffset = XhcGetCapabilityAddr (Xhc, XHC_CAP_USB_DEBUG);
+
+ DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: Capability length 0x%x\n",
Xhc->CapLength));
+ DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: HcSParams1 0x%x\n", Xhc->HcSParams1));
DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: HcSParams2 0x%x\n", Xhc->HcSParams2));
DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: HcCParams 0x%x\n", Xhc->HcCParams));
- DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: DBOff 0x%x\n", Xhc->DBOff));
- DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: RTSOff 0x%x\n", Xhc->RTSOff));
- DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: UsbLegSupOffset 0x%x\n",
Xhc->UsbLegSupOffset));
-
+ DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: DBOff 0x%x\n", Xhc->DBOff));
+ DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: RTSOff 0x%x\n", Xhc->RTSOff));
+ DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: UsbLegSupOffset 0x%x\n",
Xhc->UsbLegSupOffset));
+ DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: DebugCapSupOffset 0x%x\n",
Xhc->DebugCapSupOffset));
+
+ //
+ // Create AsyncRequest Polling Timer
//
- // Create AsyncRequest Polling Timer
- //
Status = gBS->CreateEvent (
EVT_TIMER | EVT_NOTIFY_SIGNAL,
TPL_CALLBACK,
Modified: branches/UDK2010.SR1/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h
===================================================================
--- branches/UDK2010.SR1/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h 2013-10-10
05:57:50 UTC (rev 14761)
+++ branches/UDK2010.SR1/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h 2013-10-10
07:37:14 UTC (rev 14762)
@@ -222,6 +222,7 @@
UINT32 MaxScratchpadBufs;
UINT32 ExtCapRegBase;
UINT32 UsbLegSupOffset;
+ UINT32 DebugCapSupOffset;
UINT64 *DCBAA;
UINT32 MaxSlotsEn;
//
Modified: branches/UDK2010.SR1/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
===================================================================
--- branches/UDK2010.SR1/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c 2013-10-10
05:57:50 UTC (rev 14761)
+++ branches/UDK2010.SR1/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c 2013-10-10
07:37:14 UTC (rev 14762)
@@ -571,16 +571,18 @@
}
/**
- Calculate the XHCI legacy support capability register offset.
+ Calculate the offset of the XHCI capability.
@param Xhc The XHCI Instance.
+ @param CapId The XHCI Capability ID.
@return The offset of XHCI legacy support capability register.
**/
UINT32
-XhcGetLegSupCapAddr (
- IN USB_XHCI_INSTANCE *Xhc
+XhcGetCapabilityAddr (
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 CapId
)
{
UINT32 ExtCapOffset;
@@ -594,7 +596,7 @@
// Check if the extended capability register's capability id is USB Legacy
Support.
//
Data = XhcReadExtCapReg (Xhc, ExtCapOffset);
- if ((Data & 0xFF) == 0x1) {
+ if ((Data & 0xFF) == CapId) {
return ExtCapOffset;
}
//
@@ -660,6 +662,8 @@
{
EFI_STATUS Status;
+ Status = EFI_SUCCESS;
+
DEBUG ((EFI_D_INFO, "XhcResetHC!\n"));
//
// Host can only be reset when it is halt. If not so, halt it
@@ -672,8 +676,12 @@
}
}
- XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET);
- Status = XhcWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE,
Timeout);
+ if (((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset) & 0xFF) !=
XHC_CAP_USB_DEBUG) ||
+ ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & BIT0)
== 0)) {
+ XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET);
+ Status = XhcWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE,
Timeout);
+ }
+
return Status;
}
Modified: branches/UDK2010.SR1/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
===================================================================
--- branches/UDK2010.SR1/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h 2013-10-10
05:57:50 UTC (rev 14761)
+++ branches/UDK2010.SR1/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h 2013-10-10
07:37:14 UTC (rev 14762)
@@ -29,6 +29,9 @@
#define USB_HUB_CLASS_CODE 0x09
#define USB_HUB_SUBCLASS_CODE 0x00
+#define XHC_CAP_USB_LEGACY 0x01
+#define XHC_CAP_USB_DEBUG 0x0A
+
//============================================//
// XHCI register offset //
//============================================//
@@ -67,6 +70,11 @@
#define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table
Base Address Register Offset
#define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer
Register Offset
+//
+// Debug registers offset
+//
+#define XHC_DC_DCCTRL 0x20
+
#define USBLEGSP_BIOS_SEMAPHORE BIT16 // HC BIOS Owned Semaphore
#define USBLEGSP_OS_SEMAPHORE BIT24 // HC OS Owned Semaphore
@@ -448,6 +456,21 @@
);
/**
+ Read XHCI extended capability register.
+
+ @param Xhc The XHCI Instance.
+ @param Offset The offset of the extended capability register.
+
+ @return The register content read
+
+**/
+UINT32
+XhcReadExtCapReg (
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
+ );
+
+/**
Whether the XHCI host controller is halted.
@param Xhc The XHCI Instance.
@@ -524,16 +547,18 @@
);
/**
- Calculate the XHCI legacy support capability register offset.
+ Calculate the offset of the XHCI capability.
@param Xhc The XHCI Instance.
+ @param CapId The XHCI Capability ID.
@return The offset of XHCI legacy support capability register.
**/
UINT32
-XhcGetLegSupCapAddr (
- IN USB_XHCI_INSTANCE *Xhc
+XhcGetCapabilityAddr (
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 CapId
);
#endif
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