Revision: 14892
http://sourceforge.net/p/edk2/code/14892
Author: jcarsey
Date: 2013-11-22 21:17:25 +0000 (Fri, 22 Nov 2013)
Log Message:
-----------
ShellPkg: Fix pci command output of Max and Current Link Speed, and ASPM
Support values to match PCIe Base Spec rev 3.0
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Chris Phillips <[email protected]>
Reviewed-by: Jaben Carsey <[email protected]>
Revision Links:
--------------
http://sourceforge.net/p/edk2/code/3
Modified Paths:
--------------
trunk/edk2/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c
trunk/edk2/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.h
Modified: trunk/edk2/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c
===================================================================
--- trunk/edk2/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c
2013-11-22 21:15:19 UTC (rev 14891)
+++ trunk/edk2/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c
2013-11-22 21:17:25 UTC (rev 14892)
@@ -4051,33 +4051,42 @@
)
{
UINT32 PcieLinkCap;
- CHAR16 *SupLinkSpeeds;
+ CHAR16 *MaxLinkSpeed;
CHAR16 *AspmValue;
PcieLinkCap = PciExpressCap->LinkCap;
- switch (PCIE_CAP_SUP_LINK_SPEEDS (PcieLinkCap)) {
+ switch (PCIE_CAP_MAX_LINK_SPEED (PcieLinkCap)) {
case 1:
- SupLinkSpeeds = L"2.5 GT/s";
+ MaxLinkSpeed = L"2.5 GT/s";
break;
case 2:
- SupLinkSpeeds = L"5.0 GT/s and 2.5 GT/s";
+ MaxLinkSpeed = L"5.0 GT/s";
break;
+ case 3:
+ MaxLinkSpeed = L"8.0 GT/s";
+ break;
default:
- SupLinkSpeeds = L"Unknown";
+ MaxLinkSpeed = L"Unknown";
break;
}
ShellPrintEx (-1, -1,
- L" Supported Link Speeds(3:0): %E%s
supported%N\r\n",
- SupLinkSpeeds
+ L" Maximum Link Speed(3:0): %E%s%N\r\n",
+ MaxLinkSpeed
);
ShellPrintEx (-1, -1,
L" Maximum Link Width(9:4): %Ex%d%N\r\n",
PCIE_CAP_MAX_LINK_WIDTH (PcieLinkCap)
);
switch (PCIE_CAP_ASPM_SUPPORT (PcieLinkCap)) {
+ case 0:
+ AspmValue = L"Not";
+ break;
case 1:
- AspmValue = L"L0s Entry";
+ AspmValue = L"L0s";
break;
+ case 2:
+ AspmValue = L"L1";
+ break;
case 3:
AspmValue = L"L0s and L1";
break;
@@ -4204,23 +4213,26 @@
)
{
UINT16 PcieLinkStatus;
- CHAR16 *SupLinkSpeeds;
+ CHAR16 *CurLinkSpeed;
PcieLinkStatus = PciExpressCap->LinkStatus;
switch (PCIE_CAP_CUR_LINK_SPEED (PcieLinkStatus)) {
case 1:
- SupLinkSpeeds = L"2.5 GT/s";
+ CurLinkSpeed = L"2.5 GT/s";
break;
case 2:
- SupLinkSpeeds = L"5.0 GT/s";
+ CurLinkSpeed = L"5.0 GT/s";
break;
+ case 3:
+ CurLinkSpeed = L"8.0 GT/s";
+ break;
default:
- SupLinkSpeeds = L"Reserved";
+ CurLinkSpeed = L"Reserved";
break;
}
ShellPrintEx (-1, -1,
L" Current Link Speed(3:0): %E%s%N\r\n",
- SupLinkSpeeds
+ CurLinkSpeed
);
ShellPrintEx (-1, -1,
L" Negotiated Link Width(9:4): %Ex%d%N\r\n",
Modified: trunk/edk2/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.h
===================================================================
--- trunk/edk2/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.h
2013-11-22 21:15:19 UTC (rev 14891)
+++ trunk/edk2/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.h
2013-11-22 21:17:25 UTC (rev 14892)
@@ -1,6 +1,7 @@
/** @file
Header file for Pci shell Debug1 function.
+ Copyright (c) 2013 Hewlett-Packard Development Company, L.P.
Copyright (c) 2005 - 2010, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD
License
@@ -157,7 +158,7 @@
//
// Link Capabilities Register
//
-#define PCIE_CAP_SUP_LINK_SPEEDS(PcieLinkCap) \
+#define PCIE_CAP_MAX_LINK_SPEED(PcieLinkCap) \
((PcieLinkCap) & 0x0f)
#define PCIE_CAP_MAX_LINK_WIDTH(PcieLinkCap) \
(((PcieLinkCap) >> 4) & 0x3f)
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