Revision: 15395
http://sourceforge.net/p/edk2/code/15395
Author: oliviermartin
Date: 2014-03-26 19:29:31 +0000 (Wed, 26 Mar 2014)
Log Message:
-----------
ArmPkg/Chipset: Added ARMv8 CPU's PartNum
PartNum is the field of MIDR that returns the CPU name.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <[email protected]>
Modified Paths:
--------------
trunk/edk2/ArmPkg/Include/Chipset/AArch64.h
trunk/edk2/ArmPkg/Include/Chipset/ArmV7.h
Modified: trunk/edk2/ArmPkg/Include/Chipset/AArch64.h
===================================================================
--- trunk/edk2/ArmPkg/Include/Chipset/AArch64.h 2014-03-26 19:28:35 UTC (rev
15394)
+++ trunk/edk2/ArmPkg/Include/Chipset/AArch64.h 2014-03-26 19:29:31 UTC (rev
15395)
@@ -1,7 +1,7 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
- Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD
License
@@ -45,10 +45,15 @@
// MIDR - Main ID Register definitions
#define ARM_CPU_TYPE_MASK 0xFFF
#define ARM_CPU_TYPE_AEMv8 0xD0F
+#define ARM_CPU_TYPE_A53 0xD03
+#define ARM_CPU_TYPE_A57 0xD07
#define ARM_CPU_TYPE_A15 0xC0F
#define ARM_CPU_TYPE_A9 0xC09
#define ARM_CPU_TYPE_A5 0xC05
+#define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )
+#define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))
+
// Hypervisor Configuration Register
#define ARM_HCR_FMO BIT3
#define ARM_HCR_IMO BIT4
@@ -116,7 +121,6 @@
VOID
);
-
VOID
EFIAPI
ArmEnableAlignmentCheck (
Modified: trunk/edk2/ArmPkg/Include/Chipset/ArmV7.h
===================================================================
--- trunk/edk2/ArmPkg/Include/Chipset/ArmV7.h 2014-03-26 19:28:35 UTC (rev
15394)
+++ trunk/edk2/ArmPkg/Include/Chipset/ArmV7.h 2014-03-26 19:29:31 UTC (rev
15395)
@@ -1,7 +1,7 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
- Copyright (c) 2011-2013, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD
License
@@ -71,10 +71,16 @@
// MIDR - Main ID Register definitions
#define ARM_CPU_TYPE_MASK 0xFFF
+#define ARM_CPU_TYPE_AEMv8 0xD0F
+#define ARM_CPU_TYPE_A53 0xD03
+#define ARM_CPU_TYPE_A57 0xD07
#define ARM_CPU_TYPE_A15 0xC0F
#define ARM_CPU_TYPE_A9 0xC09
#define ARM_CPU_TYPE_A5 0xC05
+#define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )
+#define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))
+
#define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 5)-1)
VOID
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