Revision: 16440
http://sourceforge.net/p/edk2/code/16440
Author: vanjeff
Date: 2014-11-25 08:13:19 +0000 (Tue, 25 Nov 2014)
Log Message:
-----------
MdeModulePkg BaseSerialPortLib16550: Correct MemoryLimit and MemoryBase offset.
Their offset in PCI-to-PCI Bridge Configuration Space.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <[email protected]>
Reviewed-by: Michael Kinney <[email protected]>
Reviewed-by: Guo Dong <[email protected]>
(Sync patch r16401 from main trunk.)
(cherry picked from commit 82503bbd8eda5d954e24ae52b98db6f28fffbf32)
Revision Links:
--------------
http://sourceforge.net/p/edk2/code/16401
Modified Paths:
--------------
branches/UDK2014.SP1/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
Modified:
branches/UDK2014.SP1/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
===================================================================
---
branches/UDK2014.SP1/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
2014-11-25 08:12:37 UTC (rev 16439)
+++
branches/UDK2014.SP1/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
2014-11-25 08:13:19 UTC (rev 16440)
@@ -244,8 +244,8 @@
// Retrieve and verify the I/O or MMIO decode window in the PCI to PCI
Bridge
//
if (PcdGetBool (PcdSerialUseMmio)) {
- MemoryLimit = PciRead16 (PciLibAddress + OFFSET_OF
(PCI_BRIDGE_CONTROL_REGISTER, MemoryLimit)) & 0xfff0;
- MemoryBase = PciRead16 (PciLibAddress + OFFSET_OF
(PCI_BRIDGE_CONTROL_REGISTER, MemoryBase)) & 0xfff0;
+ MemoryLimit = PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01,
Bridge.MemoryLimit)) & 0xfff0;
+ MemoryBase = PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01,
Bridge.MemoryBase)) & 0xfff0;
//
// If PCI Bridge MMIO window is disabled, then return 0
@@ -263,17 +263,17 @@
ParentMemoryBase = MemoryBase;
ParentMemoryLimit = MemoryLimit;
} else {
- IoLimit = PciRead8 (PciLibAddress + OFFSET_OF
(PCI_BRIDGE_CONTROL_REGISTER, IoLimit));
+ IoLimit = PciRead8 (PciLibAddress + OFFSET_OF (PCI_TYPE01,
Bridge.IoLimit));
if ((IoLimit & PCI_BRIDGE_32_BIT_IO_SPACE ) == 0) {
IoLimit = IoLimit >> 4;
} else {
- IoLimit = (PciRead16 (PciLibAddress + OFFSET_OF
(PCI_BRIDGE_CONTROL_REGISTER, IoLimitUpper16)) << 4) | (IoLimit >> 4);
+ IoLimit = (PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01,
Bridge.IoLimitUpper16)) << 4) | (IoLimit >> 4);
}
- IoBase = PciRead8 (PciLibAddress + OFFSET_OF
(PCI_BRIDGE_CONTROL_REGISTER, IoBase));
+ IoBase = PciRead8 (PciLibAddress + OFFSET_OF (PCI_TYPE01,
Bridge.IoBase));
if ((IoBase & PCI_BRIDGE_32_BIT_IO_SPACE ) == 0) {
IoBase = IoBase >> 4;
} else {
- IoBase = (PciRead16 (PciLibAddress + OFFSET_OF
(PCI_BRIDGE_CONTROL_REGISTER, IoBaseUpper16)) << 4) | (IoBase >> 4);
+ IoBase = (PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01,
Bridge.IoBaseUpper16)) << 4) | (IoBase >> 4);
}
//
------------------------------------------------------------------------------
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