Revision: 16599
http://sourceforge.net/p/edk2/code/16599
Author: zwei4
Date: 2015-01-12 09:37:20 +0000 (Mon, 12 Jan 2015)
Log Message:
-----------
Upload BSD-licensed Vlv2TbltDevicePkg and Vlv2DeviceRefCodePkg to
https://svn.code.sf.net/p/edk2/code/trunk/edk2/,
which are for MinnowBoard MAX open source project.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: David Wei <[email protected]>
Reviewed-by: Mike Wu <[email protected]>
Reviewed-by: Hot Tian <[email protected]>
Added Paths:
-----------
trunk/edk2/Vlv2DeviceRefCodePkg/
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/98_LINK.ASL
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/AcpiTablePlatform.h
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/AcpiTables.inf
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/CPU.asl
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/DSDT.ASL
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Facp/
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Facp/Facp.aslc
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Facs/
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Facs/Facs.aslc
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/GloblNvs.asl
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Gpe.asl
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/HOST_BUS.ASL
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Hpet/
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Hpet/Hpet.aslc
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/INTELGFX.ASL
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/INTELISPDev2.ASL
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOGBDA.ASL
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOMOBF.ASL
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOSBCB.ASL
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOpRn.ASL
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IoTVirtualDevice.asl
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/LPC_DEV.ASL
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/LpcB.asl
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Lpit/
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Lpit/Lpit.aslc
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Madt/
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Madt/Madt.h
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Madt/Madt30.aslc
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Mcfg/
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Mcfg/Mcfg.aslc
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PCI_DRC.ASL
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Pch.asl
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchAudio.asl
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchEhci.asl
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchLpss.asl
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchPcie.asl
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchScc.asl
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchSmb.asl
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchXhci.asl
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PciTree.asl
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Platform.asl
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/RTD3.asl
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/THERMAL.ASL
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/UsbSbd.asl
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Video.asl
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Vlv.asl
trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/token.asl
trunk/edk2/Vlv2DeviceRefCodePkg/Include/
trunk/edk2/Vlv2DeviceRefCodePkg/Include/Guid/
trunk/edk2/Vlv2DeviceRefCodePkg/Include/Guid/Vlv2DeviceRefCodePkgTokenSpace.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Guid/
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Guid/PowerManagementAcpiTableStorage.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Ppi/
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Ppi/VlvPolicy.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Protocol/
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Protocol/PpmPlatformPolicy.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Types.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/PowerManagementAcpiTables.inf
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/ApCst.asl
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/ApIst.asl
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/ApTst.asl
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/Cpu0Cst.asl
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/Cpu0Ist.asl
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/Cpu0Tst.asl
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/CpuPm.asl
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/PlatformBaseAddresses.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/Capsule.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/PlatformMemoryRange.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/PlatformMemorySize.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/SmmAccess.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/VlvMmioPolicy.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/VlvPeiInit.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/VlvPolicy.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Protocol/
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Protocol/IgdOpRegion.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Protocol/MemInfo.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Protocol/PlatformGopPolicy.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Protocol/VlvPlatformPolicy.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Valleyview.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/VlvAccess.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/VlvCommonDefinitions.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Guid/
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Guid/PchInitVar.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Guid/SataControllerGuid.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Guid/SmbusArpMap.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Guid/Vlv2Variable.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/IndustryStandard/
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/IndustryStandard/CeAta.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/IndustryStandard/Mmc.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/IndustryStandard/SdCard.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Library/
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Library/I2CLib.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Library/PchPlatformLib.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchAccess.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchCommonDefinitions.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsHda.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsLpss.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsPcie.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsPcu.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsRcrb.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSata.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsScc.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSmbus.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSpi.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsUsb.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PchInit.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PchPeiInit.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PchPlatformPolicy.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PchUsbPolicy.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PeiBlockIo.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/Sdhc.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/SmbusPolicy.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/Spi.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/ActiveBios.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/ActiveBiosProtocol.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/DxePchPolicyUpdateProtocol.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/EmmcCardInfoProtocol.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/Gpio.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/HwWatchdogTimer.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/I2cBus.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchExtendedReset.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchInfo.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchPlatformPolicy.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchReset.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchS3Support.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SdHostIo.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SmbiosSlotPopulation.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SmmIchnDispatchEx.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SmmSmbus.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/Spi.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/TcoReset.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Rsci.h
trunk/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/TianoApi.h
trunk/edk2/Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
trunk/edk2/Vlv2TbltDevicePkg/
trunk/edk2/Vlv2TbltDevicePkg/AcpiPlatform/
trunk/edk2/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatform.c
trunk/edk2/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatform.h
trunk/edk2/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatform.inf
trunk/edk2/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatformHooks.c
trunk/edk2/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatformHooks.h
trunk/edk2/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatformHooksLib.h
trunk/edk2/Vlv2TbltDevicePkg/AcpiPlatform/Osfr.h
trunk/edk2/Vlv2TbltDevicePkg/Application/
trunk/edk2/Vlv2TbltDevicePkg/Application/FirmwareUpdate/
trunk/edk2/Vlv2TbltDevicePkg/Application/FirmwareUpdate/FirmwareUpdate.c
trunk/edk2/Vlv2TbltDevicePkg/Application/FirmwareUpdate/FirmwareUpdate.h
trunk/edk2/Vlv2TbltDevicePkg/Application/FirmwareUpdate/FirmwareUpdate.inf
trunk/edk2/Vlv2TbltDevicePkg/Application/FirmwareUpdate/FirmwareUpdateStrings.uni
trunk/edk2/Vlv2TbltDevicePkg/BfmLib.exe
trunk/edk2/Vlv2TbltDevicePkg/BiosIdD.env
trunk/edk2/Vlv2TbltDevicePkg/BiosIdR.env
trunk/edk2/Vlv2TbltDevicePkg/BiosIdx64D.env
trunk/edk2/Vlv2TbltDevicePkg/BiosIdx64R.env
trunk/edk2/Vlv2TbltDevicePkg/BootScriptSaveDxe/
trunk/edk2/Vlv2TbltDevicePkg/BootScriptSaveDxe/BootScriptSaveDxe.inf
trunk/edk2/Vlv2TbltDevicePkg/BootScriptSaveDxe/InternalBootScriptSave.h
trunk/edk2/Vlv2TbltDevicePkg/BootScriptSaveDxe/ScriptSave.c
trunk/edk2/Vlv2TbltDevicePkg/Build_IFWI.bat
trunk/edk2/Vlv2TbltDevicePkg/Build_IFWI.sh
trunk/edk2/Vlv2TbltDevicePkg/FCE.exe
trunk/edk2/Vlv2TbltDevicePkg/FspAzaliaConfigData/
trunk/edk2/Vlv2TbltDevicePkg/FspAzaliaConfigData/AzaliaConfig.bin
trunk/edk2/Vlv2TbltDevicePkg/FspSupport/
trunk/edk2/Vlv2TbltDevicePkg/FspSupport/BootModePei/
trunk/edk2/Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModePei.c
trunk/edk2/Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModePei.inf
trunk/edk2/Vlv2TbltDevicePkg/FspSupport/Library/
trunk/edk2/Vlv2TbltDevicePkg/FspSupport/Library/PeiFspHobProcessLibVlv2/
trunk/edk2/Vlv2TbltDevicePkg/FspSupport/Library/PeiFspHobProcessLibVlv2/FspHobProcessLibVlv2.c
trunk/edk2/Vlv2TbltDevicePkg/FspSupport/Library/PeiFspHobProcessLibVlv2/FspHobProcessLibVlv2.inf
trunk/edk2/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/
trunk/edk2/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/FspPlatformSecLibVlv2.c
trunk/edk2/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/FspPlatformSecLibVlv2.inf
trunk/edk2/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/
trunk/edk2/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/AsmSaveSecContext.asm
trunk/edk2/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/Fsp.inc
trunk/edk2/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/PeiCoreEntry.asm
trunk/edk2/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/SecEntry.asm
trunk/edk2/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/Stack.S
trunk/edk2/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/Stack.asm
trunk/edk2/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/PlatformInit.c
trunk/edk2/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SaveSecContext.c
trunk/edk2/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SecGetPerformance.c
trunk/edk2/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SecPlatformInformation.c
trunk/edk2/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SecRamInitData.c
trunk/edk2/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SecTempRamSupport.c
trunk/edk2/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/UartInit.c
trunk/edk2/Vlv2TbltDevicePkg/FvInfoPei/
trunk/edk2/Vlv2TbltDevicePkg/FvInfoPei/FvInfoPei.c
trunk/edk2/Vlv2TbltDevicePkg/FvInfoPei/FvInfoPei.inf
trunk/edk2/Vlv2TbltDevicePkg/FvbRuntimeDxe/
trunk/edk2/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbInfo.c
trunk/edk2/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbRuntimeDxe.inf
trunk/edk2/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbService.c
trunk/edk2/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbService.h
trunk/edk2/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbServiceDxe.c
trunk/edk2/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbServiceSmm.c
trunk/edk2/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmm.inf
trunk/edk2/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmmCommon.h
trunk/edk2/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmmDxe.c
trunk/edk2/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmmDxe.h
trunk/edk2/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmmDxe.inf
trunk/edk2/Vlv2TbltDevicePkg/GenBiosId
trunk/edk2/Vlv2TbltDevicePkg/GenBiosId.exe
trunk/edk2/Vlv2TbltDevicePkg/Include/
trunk/edk2/Vlv2TbltDevicePkg/Include/AlertStandardFormatTable.h
trunk/edk2/Vlv2TbltDevicePkg/Include/ChipsetAccess.h
trunk/edk2/Vlv2TbltDevicePkg/Include/CommonIncludes.h
trunk/edk2/Vlv2TbltDevicePkg/Include/CpuType.h
trunk/edk2/Vlv2TbltDevicePkg/Include/FileHandleLib.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Guid/
trunk/edk2/Vlv2TbltDevicePkg/Include/Guid/AcpiTableStorage.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Guid/AlertStandardFormat.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Guid/BiosId.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Guid/BoardFeatures.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Guid/EfiVpdData.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Guid/FirmwareId.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Guid/HwWatchdogTimerHob.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Guid/IdccData.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Guid/ItkData.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Guid/MemoryConfigData.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Guid/OsSelection.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Guid/PciLanInfo.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Guid/PlatformCpuInfo.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Guid/PlatformInfo.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Guid/SensorInfoVariable.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Guid/SetupVariable.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Hpet.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Library/
trunk/edk2/Vlv2TbltDevicePkg/Include/Library/BiosIdLib.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Library/CpuIA32.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Library/EfiRegTableLib.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Library/Esrt.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Library/Fd.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Library/FlashDeviceLib.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Library/I2cMmioConfigLib.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Library/I2cPort_platform.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Library/PlatformFsaLib.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Library/PlatformFspLib.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Library/SpiFlash.H
trunk/edk2/Vlv2TbltDevicePkg/Include/Library/StallSmmLib.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Library/UsbDeviceModeLib.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Mcfg.h
trunk/edk2/Vlv2TbltDevicePkg/Include/McfgTable.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Platform.h
trunk/edk2/Vlv2TbltDevicePkg/Include/PlatformBootMode.h
trunk/edk2/Vlv2TbltDevicePkg/Include/PlatformDefinitions.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Ppi/
trunk/edk2/Vlv2TbltDevicePkg/Include/Ppi/MfgMemoryTest.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Ppi/Sha256Hash.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Ppi/Speaker.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Ppi/UsbController.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Protocol/
trunk/edk2/Vlv2TbltDevicePkg/Include/Protocol/CK505ClockPlatformInfo.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Protocol/EnhancedSpeedstep.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Protocol/GlobalNvsArea.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Protocol/HwWatchdogTimer.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Protocol/I2cAcpi.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Protocol/I2cBus.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Protocol/I2cBusMcg.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Protocol/I2cHostMcg.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Protocol/I2cMasterMcg.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Protocol/I2cSlave.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Protocol/LpcWpc83627Policy.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Protocol/LpcWpce791Policy.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Protocol/MmioDevice.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Protocol/Observable.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Protocol/PlatformGopPolicy.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Protocol/PlatformIdeInit.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Protocol/SetupMode.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Protocol/SmbiosSlotPopulation.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Protocol/Speaker.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Protocol/TcoReset.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Protocol/TpmMp.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Protocol/UsbPolicy.h
trunk/edk2/Vlv2TbltDevicePkg/Include/Protocol/VlvPlatformPolicy.h
trunk/edk2/Vlv2TbltDevicePkg/Include/SetupMode.h
trunk/edk2/Vlv2TbltDevicePkg/IntelGopDepex/
trunk/edk2/Vlv2TbltDevicePkg/IntelGopDepex/IntelGopDriver.depex
trunk/edk2/Vlv2TbltDevicePkg/Library/
trunk/edk2/Vlv2TbltDevicePkg/Library/BiosIdLib/
trunk/edk2/Vlv2TbltDevicePkg/Library/BiosIdLib/BiosIdLib.c
trunk/edk2/Vlv2TbltDevicePkg/Library/BiosIdLib/BiosIdLib.inf
trunk/edk2/Vlv2TbltDevicePkg/Library/CpuIA32Lib/
trunk/edk2/Vlv2TbltDevicePkg/Library/CpuIA32Lib/CpuIA32Lib.inf
trunk/edk2/Vlv2TbltDevicePkg/Library/CpuIA32Lib/EfiCpuVersion.c
trunk/edk2/Vlv2TbltDevicePkg/Library/CpuIA32Lib/IA32/
trunk/edk2/Vlv2TbltDevicePkg/Library/CpuIA32Lib/IA32/CpuIA32.S
trunk/edk2/Vlv2TbltDevicePkg/Library/CpuIA32Lib/IA32/CpuIA32.asm
trunk/edk2/Vlv2TbltDevicePkg/Library/CpuIA32Lib/IA32/CpuIA32.c
trunk/edk2/Vlv2TbltDevicePkg/Library/CpuIA32Lib/X64/
trunk/edk2/Vlv2TbltDevicePkg/Library/CpuIA32Lib/X64/Cpu.S
trunk/edk2/Vlv2TbltDevicePkg/Library/CpuIA32Lib/X64/Cpu.asm
trunk/edk2/Vlv2TbltDevicePkg/Library/EfiRegTableLib/
trunk/edk2/Vlv2TbltDevicePkg/Library/EfiRegTableLib/EfiRegTableLib.c
trunk/edk2/Vlv2TbltDevicePkg/Library/EfiRegTableLib/EfiRegTableLib.inf
trunk/edk2/Vlv2TbltDevicePkg/Library/FlashDeviceLib/
trunk/edk2/Vlv2TbltDevicePkg/Library/FlashDeviceLib/FlashDeviceLib.c
trunk/edk2/Vlv2TbltDevicePkg/Library/FlashDeviceLib/FlashDeviceLib.inf
trunk/edk2/Vlv2TbltDevicePkg/Library/FlashDeviceLib/SpiChipDefinitions.h
trunk/edk2/Vlv2TbltDevicePkg/Library/I2CLib/
trunk/edk2/Vlv2TbltDevicePkg/Library/I2CLib/I2CLib.c
trunk/edk2/Vlv2TbltDevicePkg/Library/I2CLib/I2CLibNull.inf
trunk/edk2/Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/
trunk/edk2/Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/CommonHeader.h
trunk/edk2/Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.c
trunk/edk2/Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf
trunk/edk2/Vlv2TbltDevicePkg/Library/MultiPlatformLib/
trunk/edk2/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardClkGens/
trunk/edk2/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardClkGens/BoardClkGens.c
trunk/edk2/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardClkGens/BoardClkGens.h
trunk/edk2/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardGpios/
trunk/edk2/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardGpios/BoardGpios.c
trunk/edk2/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardGpios/BoardGpios.h
trunk/edk2/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardJumpers/
trunk/edk2/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardJumpers/BoardJumpers.c
trunk/edk2/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardJumpers/BoardJumpers.h
trunk/edk2/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardOemIds/
trunk/edk2/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardOemIds/BoardOemIds.c
trunk/edk2/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardOemIds/BoardOemIds.h
trunk/edk2/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardSsidSvid/
trunk/edk2/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardSsidSvid/BoardSsidSvid.c
trunk/edk2/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardSsidSvid/BoardSsidSvid.h
trunk/edk2/Vlv2TbltDevicePkg/Library/MultiPlatformLib/MultiPlatformLib.c
trunk/edk2/Vlv2TbltDevicePkg/Library/MultiPlatformLib/MultiPlatformLib.h
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trunk/edk2/Vlv2TbltDevicePkg/Library/MultiPlatformLib/PlatformInfoHob.c
trunk/edk2/Vlv2TbltDevicePkg/Library/PchPlatformLib/
trunk/edk2/Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLib.inf
trunk/edk2/Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLibrary.c
trunk/edk2/Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLibrary.h
trunk/edk2/Vlv2TbltDevicePkg/Library/PchSmmLib/
trunk/edk2/Vlv2TbltDevicePkg/Library/PchSmmLib/CommonHeader.h
trunk/edk2/Vlv2TbltDevicePkg/Library/PchSmmLib/PchSmmLib.c
trunk/edk2/Vlv2TbltDevicePkg/Library/PchSmmLib/PchSmmLib.inf
trunk/edk2/Vlv2TbltDevicePkg/Library/PlatformBdsLib/
trunk/edk2/Vlv2TbltDevicePkg/Library/PlatformBdsLib/BdsPlatform.c
trunk/edk2/Vlv2TbltDevicePkg/Library/PlatformBdsLib/BdsPlatform.h
trunk/edk2/Vlv2TbltDevicePkg/Library/PlatformBdsLib/PlatformBdsLib.inf
trunk/edk2/Vlv2TbltDevicePkg/Library/PlatformBdsLib/PlatformData.c
trunk/edk2/Vlv2TbltDevicePkg/Library/PlatformCmosLib/
trunk/edk2/Vlv2TbltDevicePkg/Library/PlatformCmosLib/PlatformCmosLib.c
trunk/edk2/Vlv2TbltDevicePkg/Library/PlatformCmosLib/PlatformCmosLib.inf
trunk/edk2/Vlv2TbltDevicePkg/Library/PlatformFspLib/
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trunk/edk2/Vlv2TbltDevicePkg/Library/PlatformFspLib/PlatformFspLib.inf
trunk/edk2/Vlv2TbltDevicePkg/Library/ResetSystemLib/
trunk/edk2/Vlv2TbltDevicePkg/Library/ResetSystemLib/ResetSystemLib.c
trunk/edk2/Vlv2TbltDevicePkg/Library/ResetSystemLib/ResetSystemLib.inf
trunk/edk2/Vlv2TbltDevicePkg/Library/SerialPortLib/
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trunk/edk2/Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.c
trunk/edk2/Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf
trunk/edk2/Vlv2TbltDevicePkg/Library/SerialPortLib/SioInit.c
trunk/edk2/Vlv2TbltDevicePkg/Library/SerialPortLib/SioInit.h
trunk/edk2/Vlv2TbltDevicePkg/Library/SmbusLib/
trunk/edk2/Vlv2TbltDevicePkg/Library/SmbusLib/CommonHeader.h
trunk/edk2/Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.c
trunk/edk2/Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf
trunk/edk2/Vlv2TbltDevicePkg/Library/StallSmmLib/
trunk/edk2/Vlv2TbltDevicePkg/Library/StallSmmLib/StallSmm.c
trunk/edk2/Vlv2TbltDevicePkg/Library/StallSmmLib/StallSmmLib.inf
trunk/edk2/Vlv2TbltDevicePkg/Logo/
trunk/edk2/Vlv2TbltDevicePkg/Logo/Logo.bmp
trunk/edk2/Vlv2TbltDevicePkg/Metronome/
trunk/edk2/Vlv2TbltDevicePkg/Metronome/LegacyMetronome.c
trunk/edk2/Vlv2TbltDevicePkg/Metronome/LegacyMetronome.h
trunk/edk2/Vlv2TbltDevicePkg/Metronome/Metronome.inf
trunk/edk2/Vlv2TbltDevicePkg/MonoStatusCode/
trunk/edk2/Vlv2TbltDevicePkg/MonoStatusCode/EfiStatusCode.h
trunk/edk2/Vlv2TbltDevicePkg/MonoStatusCode/MonoStatusCode.c
trunk/edk2/Vlv2TbltDevicePkg/MonoStatusCode/MonoStatusCode.h
trunk/edk2/Vlv2TbltDevicePkg/MonoStatusCode/MonoStatusCode.inf
trunk/edk2/Vlv2TbltDevicePkg/MonoStatusCode/PeiPostCode.c
trunk/edk2/Vlv2TbltDevicePkg/MonoStatusCode/PlatformStatusCode.c
trunk/edk2/Vlv2TbltDevicePkg/MonoStatusCode/PlatformStatusCode.h
trunk/edk2/Vlv2TbltDevicePkg/Override/
trunk/edk2/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/
trunk/edk2/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/
trunk/edk2/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/
trunk/edk2/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/BdsBoot.c
trunk/edk2/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/BdsConnect.c
trunk/edk2/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/BdsConsole.c
trunk/edk2/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/BdsMisc.c
trunk/edk2/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/DevicePath.c
trunk/edk2/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
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trunk/edk2/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/InternalBdsLib.h
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trunk/edk2/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/String.c
trunk/edk2/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/String.h
trunk/edk2/Vlv2TbltDevicePkg/Override/MdeModulePkg/
trunk/edk2/Vlv2TbltDevicePkg/Override/MdeModulePkg/Universal/
trunk/edk2/Vlv2TbltDevicePkg/Override/MdeModulePkg/Universal/Console/
trunk/edk2/Vlv2TbltDevicePkg/Override/MdeModulePkg/Universal/Console/ConSplitterDxe/
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trunk/edk2/Vlv2TbltDevicePkg/Override/MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitter.c
trunk/edk2/Vlv2TbltDevicePkg/Override/MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitter.h
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trunk/edk2/Vlv2TbltDevicePkg/Override/MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterGraphics.c
trunk/edk2/Vlv2TbltDevicePkg/PciPlatform/
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trunk/edk2/Vlv2TbltDevicePkg/PciPlatform/PciPlatform.c
trunk/edk2/Vlv2TbltDevicePkg/PciPlatform/PciPlatform.h
trunk/edk2/Vlv2TbltDevicePkg/PciPlatform/PciPlatform.inf
trunk/edk2/Vlv2TbltDevicePkg/PlatformCpuInfoDxe/
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trunk/edk2/Vlv2TbltDevicePkg/PlatformCpuInfoDxe/PlatformCpuInfoDxe.h
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trunk/edk2/Vlv2TbltDevicePkg/PlatformDxe/
trunk/edk2/Vlv2TbltDevicePkg/PlatformDxe/AzaliaVerbTable.h
trunk/edk2/Vlv2TbltDevicePkg/PlatformDxe/BoardId.c
trunk/edk2/Vlv2TbltDevicePkg/PlatformDxe/BoardIdDecode.c
trunk/edk2/Vlv2TbltDevicePkg/PlatformDxe/BoardIdDecode.h
trunk/edk2/Vlv2TbltDevicePkg/PlatformDxe/ClockControl.c
trunk/edk2/Vlv2TbltDevicePkg/PlatformDxe/Configuration.h
trunk/edk2/Vlv2TbltDevicePkg/PlatformDxe/ExI.c
trunk/edk2/Vlv2TbltDevicePkg/PlatformDxe/IchPlatformPolicy.c
trunk/edk2/Vlv2TbltDevicePkg/PlatformDxe/IchRegTable.c
trunk/edk2/Vlv2TbltDevicePkg/PlatformDxe/IchTcoReset.c
trunk/edk2/Vlv2TbltDevicePkg/PlatformDxe/IdccInfo.c
trunk/edk2/Vlv2TbltDevicePkg/PlatformDxe/LegacySpeaker.c
trunk/edk2/Vlv2TbltDevicePkg/PlatformDxe/LegacySpeaker.h
trunk/edk2/Vlv2TbltDevicePkg/PlatformDxe/Observable/
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trunk/edk2/Vlv2TbltDevicePkg/PlatformDxe/Observable/Observable.h
trunk/edk2/Vlv2TbltDevicePkg/PlatformDxe/PciBus.h
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trunk/edk2/Vlv2TbltDevicePkg/PlatformDxe/Platform.c
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trunk/edk2/Vlv2TbltDevicePkg/PlatformDxe/SioPlatformPolicy.c
trunk/edk2/Vlv2TbltDevicePkg/PlatformDxe/SlotConfig.c
trunk/edk2/Vlv2TbltDevicePkg/PlatformDxe/SlotConfig.h
trunk/edk2/Vlv2TbltDevicePkg/PlatformGopPolicy/
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trunk/edk2/Vlv2TbltDevicePkg/PlatformInfoDxe/
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trunk/edk2/Vlv2TbltDevicePkg/PlatformInitPei/
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trunk/edk2/Vlv2TbltDevicePkg/PlatformInitPei/CpuInitPeim.c
trunk/edk2/Vlv2TbltDevicePkg/PlatformInitPei/Dimm.c
trunk/edk2/Vlv2TbltDevicePkg/PlatformInitPei/FlashMap.c
trunk/edk2/Vlv2TbltDevicePkg/PlatformInitPei/LegacySpeaker.c
trunk/edk2/Vlv2TbltDevicePkg/PlatformInitPei/LegacySpeaker.h
trunk/edk2/Vlv2TbltDevicePkg/PlatformInitPei/MchInit.c
trunk/edk2/Vlv2TbltDevicePkg/PlatformInitPei/MemoryCallback.c
trunk/edk2/Vlv2TbltDevicePkg/PlatformInitPei/MemoryPeim.c
trunk/edk2/Vlv2TbltDevicePkg/PlatformInitPei/PchInitPeim.c
trunk/edk2/Vlv2TbltDevicePkg/PlatformInitPei/PlatformEarlyInit.c
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trunk/edk2/Vlv2TbltDevicePkg/PlatformInitPei/Recovery.c
trunk/edk2/Vlv2TbltDevicePkg/PlatformInitPei/Stall.c
trunk/edk2/Vlv2TbltDevicePkg/PlatformPei/
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trunk/edk2/Vlv2TbltDevicePkg/PlatformPei/CommonHeader.h
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trunk/edk2/Vlv2TbltDevicePkg/PlatformSetupDxe/Main.vfi
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trunk/edk2/Vlv2TbltDevicePkg/PlatformSetupDxe/Security.vfi
trunk/edk2/Vlv2TbltDevicePkg/PlatformSetupDxe/SetupFunctions.c
trunk/edk2/Vlv2TbltDevicePkg/PlatformSetupDxe/SetupInfoRecords.c
trunk/edk2/Vlv2TbltDevicePkg/PlatformSetupDxe/SouthClusterConfig.vfi
trunk/edk2/Vlv2TbltDevicePkg/PlatformSetupDxe/SystemComponent.vfi
trunk/edk2/Vlv2TbltDevicePkg/PlatformSetupDxe/Thermal.vfi
trunk/edk2/Vlv2TbltDevicePkg/PlatformSetupDxe/UnCore.vfi
trunk/edk2/Vlv2TbltDevicePkg/PlatformSetupDxe/UqiList.uni
trunk/edk2/Vlv2TbltDevicePkg/PlatformSetupDxe/Vfr.vfr
trunk/edk2/Vlv2TbltDevicePkg/PlatformSetupDxe/VfrStrings.uni
trunk/edk2/Vlv2TbltDevicePkg/PlatformSmm/
trunk/edk2/Vlv2TbltDevicePkg/PlatformSmm/Platform.c
trunk/edk2/Vlv2TbltDevicePkg/PlatformSmm/PlatformSmm.inf
trunk/edk2/Vlv2TbltDevicePkg/PlatformSmm/S3Save.c
trunk/edk2/Vlv2TbltDevicePkg/PlatformSmm/SmmPlatform.h
trunk/edk2/Vlv2TbltDevicePkg/PlatformSmm/SmmScriptSave.c
trunk/edk2/Vlv2TbltDevicePkg/PlatformSmm/SmmScriptSave.h
trunk/edk2/Vlv2TbltDevicePkg/PpmPolicy/
trunk/edk2/Vlv2TbltDevicePkg/PpmPolicy/PpmPolicy.c
trunk/edk2/Vlv2TbltDevicePkg/PpmPolicy/PpmPolicy.h
trunk/edk2/Vlv2TbltDevicePkg/PpmPolicy/PpmPolicy.inf
trunk/edk2/Vlv2TbltDevicePkg/SaveMemoryConfig/
trunk/edk2/Vlv2TbltDevicePkg/SaveMemoryConfig/SaveMemoryConfig.c
trunk/edk2/Vlv2TbltDevicePkg/SaveMemoryConfig/SaveMemoryConfig.h
trunk/edk2/Vlv2TbltDevicePkg/SaveMemoryConfig/SaveMemoryConfig.inf
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/CommonHeader.h
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBaseBoardManufacturer.uni
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBaseBoardManufacturerData.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBaseBoardManufacturerFunction.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBiosVendor.uni
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBiosVendorData.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBiosVendorFunction.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBootInformationData.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBootInformationFunction.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscChassisManufacturer.uni
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscChassisManufacturerData.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscChassisManufacturerFunction.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscMemoryDevice.uni
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscMemoryDeviceData.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscMemoryDeviceFunction.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscNumberOfInstallableLanguagesData.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscNumberOfInstallableLanguagesFunction.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemString.uni
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemStringData.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemStringFunction.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x90.uni
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x90Data.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x90Function.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x94.uni
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x94Data.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x94Function.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOnboardDevice.uni
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOnboardDeviceData.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOnboardDeviceFunction.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPhysicalArray.uni
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPhysicalArrayData.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPhysicalArrayFunction.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPortInternalConnectorDesignator.uni
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPortInternalConnectorDesignatorData.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPortInternalConnectorDesignatorFunction.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorCache.uni
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorCacheData.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorCacheFunction.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorInformation.uni
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorInformationData.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorInformationFunction.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscResetCapabilitiesData.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscResetCapabilitiesFunction.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSubclassDriver.h
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSubclassDriver.uni
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSubclassDriverDataTable.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSubclassDriverEntryPoint.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemLanguageString.uni
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemLanguageStringData.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemLanguageStringFunction.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemManufacturer.uni
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemManufacturerData.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemManufacturerFunction.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemOptionString.uni
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemOptionStringData.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemOptionStringFunction.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemSlotDesignation.uni
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemSlotDesignationData.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemSlotDesignationFunction.c
trunk/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/SmBiosMiscDxe.inf
trunk/edk2/Vlv2TbltDevicePkg/SmmSwDispatch2OnSmmSwDispatchThunk/
trunk/edk2/Vlv2TbltDevicePkg/SmmSwDispatch2OnSmmSwDispatchThunk/SmmSwDispatch2OnSmmSwDispatchThunk.c
trunk/edk2/Vlv2TbltDevicePkg/SmmSwDispatch2OnSmmSwDispatchThunk/SmmSwDispatch2OnSmmSwDispatchThunk.inf
trunk/edk2/Vlv2TbltDevicePkg/SmramSaveInfoHandlerSmm/
trunk/edk2/Vlv2TbltDevicePkg/SmramSaveInfoHandlerSmm/SmramSaveInfoHandlerSmm.c
trunk/edk2/Vlv2TbltDevicePkg/SmramSaveInfoHandlerSmm/SmramSaveInfoHandlerSmm.inf
trunk/edk2/Vlv2TbltDevicePkg/Stitch/
trunk/edk2/Vlv2TbltDevicePkg/Stitch/Gcc/
trunk/edk2/Vlv2TbltDevicePkg/Stitch/Gcc/NvStorageFtwSpare.bin
trunk/edk2/Vlv2TbltDevicePkg/Stitch/Gcc/NvStorageFtwWorking.bin
trunk/edk2/Vlv2TbltDevicePkg/Stitch/Gcc/NvStorageVariable.bin
trunk/edk2/Vlv2TbltDevicePkg/Stitch/IFWIHeader/
trunk/edk2/Vlv2TbltDevicePkg/Stitch/IFWIHeader/IFWI_HEADER.bin
trunk/edk2/Vlv2TbltDevicePkg/Stitch/IFWIHeader/Vacant.bin
trunk/edk2/Vlv2TbltDevicePkg/Stitch/IFWIStitch.bat
trunk/edk2/Vlv2TbltDevicePkg/Stitch/MNW2_Stitch_Config.txt
trunk/edk2/Vlv2TbltDevicePkg/UiApp/
trunk/edk2/Vlv2TbltDevicePkg/UiApp/FrontPage.c
trunk/edk2/Vlv2TbltDevicePkg/UiApp/UiApp.inf
trunk/edk2/Vlv2TbltDevicePkg/VlvPlatformInitDxe/
trunk/edk2/Vlv2TbltDevicePkg/VlvPlatformInitDxe/IgdOpRegion.c
trunk/edk2/Vlv2TbltDevicePkg/VlvPlatformInitDxe/IgdOpRegion.h
trunk/edk2/Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInit.c
trunk/edk2/Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInit.h
trunk/edk2/Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInitDxe.inf
trunk/edk2/Vlv2TbltDevicePkg/Wpce791/
trunk/edk2/Vlv2TbltDevicePkg/Wpce791/LpcDriver.c
trunk/edk2/Vlv2TbltDevicePkg/Wpce791/LpcDriver.h
trunk/edk2/Vlv2TbltDevicePkg/Wpce791/LpcIsaAcpi.c
trunk/edk2/Vlv2TbltDevicePkg/Wpce791/LpcIsaAcpi.h
trunk/edk2/Vlv2TbltDevicePkg/Wpce791/LpcSio.c
trunk/edk2/Vlv2TbltDevicePkg/Wpce791/LpcSio.h
trunk/edk2/Vlv2TbltDevicePkg/Wpce791/Wpce791.inf
trunk/edk2/Vlv2TbltDevicePkg/bldX64.bat
trunk/edk2/Vlv2TbltDevicePkg/bld_vlv.bat
trunk/edk2/Vlv2TbltDevicePkg/bld_vlv.sh
trunk/edk2/Vlv2TbltDevicePkg/cln.sh
Added: trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/98_LINK.ASL
===================================================================
--- trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/98_LINK.ASL
(rev 0)
+++ trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/98_LINK.ASL 2015-01-12
09:37:20 UTC (rev 16599)
@@ -0,0 +1,623 @@
+/**************************************************************************;
+;* *;
+;* *;
+;* Intel Corporation - ACPI Reference Code for the Baytrail *;
+;* Family of Customer Reference Boards. *;
+;* *;
+;* *;
+;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *;
+;
+; This program and the accompanying materials are licensed and made available
under
+; the terms and conditions of the BSD License that accompanies this
distribution.
+; The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;* *;
+;* *;
+;**************************************************************************/
+
+
+
+// Use this information when determining the Possible IRQs that can be
+// used in a given system.
+//
+// The following IRQs are always in use by legacy devices:
+// 0 = System Timer
+// 2 = 8259 PIC
+// 8 = RTC
+// 9 = SCI Interrupt (It may be used, we choose not to)
+// 13 = Co-processor Error
+//
+// The following may be in use by legacy devices:
+// 1 = If using PS/2 Keyboard
+// 3 = If COMx Port Enabled and IRQ = 3
+// 4 = If COMx Port Enabled and IRQ = 4
+// 5 = If LPT Port Enabled and IRQ = 5
+// 6 = If FDC Enabled
+// 7 = If LPT Port Enabled and IRQ = 7
+// 12 = If using PS/2 Mouse
+// 14 = Primary IDE (If populated and in Compatibility Mode)
+// 15 = Secondary IDE (If populated and in Compatibility Mode)
+//
+// The following will never be in use by legacy devices:
+// 10 = Assign to PARC, PCRC, PERC, PGRC
+// 11 = Assign to PBRC, PDRC, PFRC, PHRC
+
+Device(LNKA) // PARC Routing Resource
+{
+ Name(_HID,EISAID("PNP0C0F")) // PCI Interrupt Link Device
+
+ Name(_UID,1) // Unique to other Link Devices
+
+ // Disable the PCI IRQ.
+
+ Method(_DIS,0,Serialized)
+ {
+ Or(PARC,0x80,PARC)
+ }
+
+ // Possible IRQ Resource Setting.
+
+ Method (_PRS, 0, Serialized)
+ {
+ return (PRSA)
+ }
+
+ // Current IRQ Resource Setting.
+
+ Method(_CRS,0,Serialized)
+ {
+ Name(RTLA,ResourceTemplate()
+ {
+ IRQ(Level,ActiveLow,Shared) {}
+ })
+
+ // Point to specific byte.
+
+ CreateWordField(RTLA,1,IRQ0)
+
+ // Zero out IRQ mask bits 0-15
+
+ Store(Zero,IRQ0)
+
+ ShiftLeft(1,And(PARC,0x0F),IRQ0)
+
+ Return(RTLA)
+ }
+
+ // Set IRQ Resource Setting.
+
+ Method(_SRS,1,Serialized)
+ {
+ // Point to the specific byte passed in
+
+ CreateWordField(Arg0,1,IRQ0)
+
+ // Determine the IRQ bit to set and store it
+
+ FindSetRightBit(IRQ0,Local0)
+ Decrement(Local0)
+ Store(Local0,PARC)
+ }
+
+ // PCI IRQ Status.
+
+ Method(_STA,0,Serialized)
+ {
+ If(And(PARC,0x80))
+ {
+ Return(0x0009)
+ }
+ Else
+ {
+ Return(0x000B)
+ }
+ }
+}
+
+Device(LNKB) // PBRC Routing Resource
+{
+ Name(_HID,EISAID("PNP0C0F"))
+
+ Name(_UID,2)
+
+ // Disable the PCI IRQ.
+
+ Method(_DIS,0,Serialized)
+ {
+ Or(PBRC,0x80,PBRC)
+ }
+
+ // Possible IRQ Resource Setting.
+
+ Method (_PRS, 0, Serialized)
+ {
+ return (PRSB)
+ }
+
+ // Current IRQ Resource Setting.
+
+ Method(_CRS,0,Serialized)
+ {
+ Name(RTLB,ResourceTemplate()
+ {
+ IRQ(Level,ActiveLow,Shared) {}
+ })
+
+ // Point to specific byte.
+
+ CreateWordField(RTLB,1,IRQ0)
+
+ // Zero out IRQ mask bits 0-15
+
+ Store(Zero,IRQ0)
+
+ ShiftLeft(1,And(PBRC,0x0F),IRQ0)
+
+ Return(RTLB)
+ }
+
+ // Set IRQ Resource Setting.
+
+ Method(_SRS,1,Serialized)
+ {
+ // Point to the specific byte passed in.
+
+ CreateWordField(Arg0,1,IRQ0)
+
+ // Determine the IRQ bit to set and store it,
+
+ FindSetRightBit(IRQ0,Local0)
+ Decrement(Local0)
+ Store(Local0,PBRC)
+ }
+
+ // PCI IRQ Status.
+
+ Method(_STA,0,Serialized)
+ {
+ If(And(PBRC,0x80))
+ {
+ Return(0x0009)
+ }
+ Else
+ {
+ Return(0x000B)
+ }
+ }
+}
+
+Device(LNKC) // PCRC Routing Resource
+{
+ Name(_HID,EISAID("PNP0C0F"))
+
+ Name(_UID,3)
+
+ // Disable the PCI IRQ.
+
+ Method(_DIS,0,Serialized)
+ {
+ Or(PCRC,0x80,PCRC)
+ }
+
+ // Possible IRQ Resource Setting.
+
+ Method (_PRS, 0, Serialized)
+ {
+ return (PRSC)
+ }
+
+ // Current IRQ Resource Setting.
+
+ Method(_CRS,0,Serialized)
+ {
+ Name(RTLC,ResourceTemplate()
+ {
+ IRQ(Level,ActiveLow,Shared) {}
+ })
+
+ // Point to specific byte.
+
+ CreateWordField(RTLC,1,IRQ0)
+
+ // Zero out IRQ mask bits 0-15
+
+ Store(Zero,IRQ0)
+
+ ShiftLeft(1,And(PCRC,0x0F),IRQ0)
+
+ Return(RTLC)
+ }
+
+ // Set IRQ Resource Setting.
+
+ Method(_SRS,1,Serialized)
+ {
+ // Point to the specific byte passed in.
+
+ CreateWordField(Arg0,1,IRQ0)
+
+ // Determine the IRQ bit to set and store it,
+
+ FindSetRightBit(IRQ0,Local0)
+ Decrement(Local0)
+ Store(Local0,PCRC)
+ }
+
+ // PCI IRQ Status.
+
+ Method(_STA,0,Serialized)
+ {
+ If(And(PCRC,0x80))
+ {
+ Return(0x0009)
+ }
+ Else
+ {
+ Return(0x000B)
+ }
+ }
+}
+
+Device(LNKD) // PDRC Routing Resource
+{
+ Name(_HID,EISAID("PNP0C0F"))
+
+ Name(_UID,4)
+
+ // Disable the PCI IRQ.
+
+ Method(_DIS,0,Serialized)
+ {
+ Or(PDRC,0x80,PDRC)
+ }
+
+ // Possible IRQ Resource Setting.
+
+ Method (_PRS, 0, Serialized)
+ {
+ return (PRSD)
+ }
+
+ // Current IRQ Resource Setting.
+
+ Method(_CRS,0,Serialized)
+ {
+ Name(RTLD,ResourceTemplate()
+ {
+ IRQ(Level,ActiveLow,Shared) {}
+ })
+
+ // Point to specific byte.
+
+ CreateWordField(RTLD,1,IRQ0)
+
+ // Zero out IRQ mask bits 0-15
+
+ Store(Zero,IRQ0)
+
+ ShiftLeft(1,And(PDRC,0x0F),IRQ0)
+
+ Return(RTLD)
+ }
+
+ // Set IRQ Resource Setting.
+
+ Method(_SRS,1,Serialized)
+ {
+ // Point to the specific byte passed in.
+
+ CreateWordField(Arg0,1,IRQ0)
+
+ // Determine the IRQ bit to set and store it,
+
+ FindSetRightBit(IRQ0,Local0)
+ Decrement(Local0)
+ Store(Local0,PDRC)
+ }
+
+ // PCI IRQ Status.
+
+ Method(_STA,0,Serialized)
+ {
+ If(And(PDRC,0x80))
+ {
+ Return(0x0009)
+ }
+ Else
+ {
+ Return(0x000B)
+ }
+ }
+}
+
+Device(LNKE) // PERC Routing Resource
+{
+ Name(_HID,EISAID("PNP0C0F"))
+
+ Name(_UID,5)
+
+ // Disable the PCI IRQ.
+
+ Method(_DIS,0,Serialized)
+ {
+ Or(PERC,0x80,PERC)
+ }
+
+ // Possible IRQ Resource Setting.
+
+ Method (_PRS, 0, Serialized)
+ {
+ return (PRSE)
+ }
+
+ // Current IRQ Resource Setting.
+
+ Method(_CRS,0,Serialized)
+ {
+ Name(RTLE,ResourceTemplate()
+ {
+ IRQ(Level,ActiveLow,Shared) {}
+ })
+
+ // Point to specific byte.
+
+ CreateWordField(RTLE,1,IRQ0)
+
+ // Zero out IRQ mask bits 0-15
+
+ Store(Zero,IRQ0)
+
+ ShiftLeft(1,And(PERC,0x0F),IRQ0)
+
+ Return(RTLE)
+ }
+
+ // Set IRQ Resource Setting.
+
+ Method(_SRS,1,Serialized)
+ {
+ // Point to the specific byte passed in
+
+ CreateWordField(Arg0,1,IRQ0)
+
+ // Determine the IRQ bit to set and store it
+
+ FindSetRightBit(IRQ0,Local0)
+ Decrement(Local0)
+ Store(Local0,PERC)
+ }
+
+ // PCI IRQ Status.
+
+ Method(_STA,0,Serialized)
+ {
+ If(And(PERC,0x80))
+ {
+ Return(0x0009)
+ }
+ Else
+ {
+ Return(0x000B)
+ }
+ }
+}
+
+Device(LNKF) // PFRC Routing Resource
+{
+ Name(_HID,EISAID("PNP0C0F"))
+
+ Name(_UID,6)
+
+ // Disable the PCI IRQ.
+
+ Method(_DIS,0,Serialized)
+ {
+ Or(PFRC,0x80,PFRC)
+ }
+
+ // Possible IRQ Resource Setting.
+
+ Method (_PRS, 0, Serialized)
+ {
+ return (PRSF)
+ }
+
+ // Current IRQ Resource Setting.
+
+ Method(_CRS,0,Serialized)
+ {
+ Name(RTLF,ResourceTemplate()
+ {
+ IRQ(Level,ActiveLow,Shared) {}
+ })
+
+ // Point to specific byte.
+
+ CreateWordField(RTLF,1,IRQ0)
+
+ // Zero out IRQ mask bits 0-15
+
+ Store(Zero,IRQ0)
+
+ ShiftLeft(1,And(PFRC,0x0F),IRQ0)
+
+ Return(RTLF)
+ }
+
+ // Set IRQ Resource Setting.
+
+ Method(_SRS,1,Serialized)
+ {
+ // Point to the specific byte passed in.
+
+ CreateWordField(Arg0,1,IRQ0)
+
+ // Determine the IRQ bit to set and store it,
+
+ FindSetRightBit(IRQ0,Local0)
+ Decrement(Local0)
+ Store(Local0,PFRC)
+ }
+
+ // PCI IRQ Status.
+
+ Method(_STA,0,Serialized)
+ {
+ If(And(PFRC,0x80))
+ {
+ Return(0x0009)
+ }
+ Else
+ {
+ Return(0x000B)
+ }
+ }
+}
+
+Device(LNKG) // PGRC Routing Resource
+{
+ Name(_HID,EISAID("PNP0C0F"))
+
+ Name(_UID,7)
+
+ // Disable the PCI IRQ.
+
+ Method(_DIS,0,Serialized)
+ {
+ Or(PGRC,0x80,PGRC)
+ }
+
+ // Possible IRQ Resource Setting.
+
+ Method (_PRS, 0, Serialized)
+ {
+ return (PRSG)
+ }
+
+ // Current IRQ Resource Setting.
+
+ Method(_CRS,0,Serialized)
+ {
+ Name(RTLG,ResourceTemplate()
+ {
+ IRQ(Level,ActiveLow,Shared) {}
+ })
+
+ // Point to specific byte.
+
+ CreateWordField(RTLG,1,IRQ0)
+
+ // Zero out IRQ mask bits 0-15
+
+ Store(Zero,IRQ0)
+
+ ShiftLeft(1,And(PGRC,0x0F),IRQ0)
+
+ Return(RTLG)
+ }
+
+ // Set IRQ Resource Setting.
+
+ Method(_SRS,1,Serialized)
+ {
+ // Point to the specific byte passed in.
+
+ CreateWordField(Arg0,1,IRQ0)
+
+ // Determine the IRQ bit to set and store it,
+
+ FindSetRightBit(IRQ0,Local0)
+ Decrement(Local0)
+ Store(Local0,PGRC)
+ }
+
+ // PCI IRQ Status.
+
+ Method(_STA,0,Serialized)
+ {
+ If(And(PGRC,0x80))
+ {
+ Return(0x0009)
+ }
+ Else
+ {
+ Return(0x000B)
+ }
+ }
+}
+
+Device(LNKH) // PHRC Routing Resource
+{
+ Name(_HID,EISAID("PNP0C0F"))
+
+ Name(_UID,8)
+
+ // Disable the PCI IRQ.
+
+ Method(_DIS,0,Serialized)
+ {
+ Or(PHRC,0x80,PHRC)
+ }
+
+ // Possible IRQ Resource Setting.
+
+ Method (_PRS, 0, Serialized)
+ {
+ return (PRSH)
+ }
+
+ // Current IRQ Resource Setting.
+
+ Method(_CRS,0,Serialized)
+ {
+ Name(RTLH,ResourceTemplate()
+ {
+ IRQ(Level,ActiveLow,Shared) {}
+ })
+
+ // Point to specific byte.
+
+ CreateWordField(RTLH,1,IRQ0)
+
+ // Zero out IRQ mask bits 0-15
+
+ Store(Zero,IRQ0)
+
+ ShiftLeft(1,And(PHRC,0x0F),IRQ0)
+
+ Return(RTLH)
+ }
+
+ // Set IRQ Resource Setting.
+
+ Method(_SRS,1,Serialized)
+ {
+ // Point to the specific byte passed in.
+
+ CreateWordField(Arg0,1,IRQ0)
+
+ // Determine the IRQ bit to set and store it,
+
+ FindSetRightBit(IRQ0,Local0)
+ Decrement(Local0)
+ Store(Local0,PHRC)
+ }
+
+ // PCI IRQ Status.
+
+ Method(_STA,0,Serialized)
+ {
+ If(And(PHRC,0x80))
+ {
+ Return(0x0009)
+ }
+ Else
+ {
+ Return(0x000B)
+ }
+ }
+}
Added: trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/AcpiTablePlatform.h
===================================================================
--- trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/AcpiTablePlatform.h
(rev 0)
+++ trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/AcpiTablePlatform.h
2015-01-12 09:37:20 UTC (rev 16599)
@@ -0,0 +1,76 @@
+/*++
+
+Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
+
+ This program and the accompanying materials are licensed and made available
under
+ the terms and conditions of the BSD License that accompanies this
distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+Module Name:
+
+ AcpiTablePlatform.h
+
+
+Abstract: File contains platform specific ACPI defines for use in ACPI tables
+
+
+--*/
+#ifndef _Platform_h_INCLUDED_
+#define _Platform_h_INCLUDED_
+
+#ifdef ECP_FLAG
+#include "EdkIIGlueDxe.h"
+#endif
+#include <IndustryStandard/Acpi.h>
+//
+// ACPI table information used to initialize tables.
+//
+#define EFI_ACPI_OEM_ID 'O','E','M','I','D',' ' // OEMID 6 bytes
long
+#define EFI_ACPI_OEM_TABLE_ID
SIGNATURE_64('O','E','M','T','A','B','L','E') // OEM table id 8 bytes long
+#define EFI_ACPI_OEM_REVISION 0x00000005
+#define EFI_ACPI_CREATOR_ID SIGNATURE_32('C','R','E','A')
+#define EFI_ACPI_CREATOR_REVISION 0x0100000D
+#define INT_MODEL 0x01
+#define PM_PROFILE EFI_ACPI_4_0_PM_PROFILE_MOBILE
+#define SCI_INT_VECTOR 0x0009
+#define SMI_CMD_IO_PORT 0x000000B2
+#define ACPI_ENABLE 0x0A0
+#define ACPI_DISABLE 0x0A1
+#define S4BIOS_REQ 0x00
+#define PSTATE_CNT 0x00
+#define PM1a_EVT_BLK 0x00000400
+#define PM1b_EVT_BLK 0x00000000
+#define PM1a_CNT_BLK 0x00000404
+#define PM1b_CNT_BLK 0x00000000
+#define PM2_CNT_BLK 0x00000450
+#define PM_TMR_BLK 0x00000408
+#define GPE0_BLK 0x00000420
+#define GPE1_BLK 0x00000000
+#define PM1_EVT_LEN 0x04
+#define PM1_CNT_LEN 0x02
+#define PM2_CNT_LEN 0x01
+#define PM_TM_LEN 0x04
+#define GPE0_BLK_LEN 0x10
+#define GPE1_BLK_LEN 0x00
+#define GPE1_BASE 0x00
+#define CST_CNT 0x00
+#define P_LVL2_LAT 0x0064
+#define P_LVL3_LAT 0x01F4
+#define FLUSH_SIZE 0x0400
+#define FLUSH_STRIDE 0x0010
+#define DUTY_OFFSET 0x01
+#define DUTY_WIDTH 0x03
+#define DAY_ALRM 0x0D
+#define MON_ALRM 0x00
+#define CENTURY 0x32
+#define FLAG ( EFI_ACPI_4_0_WBINVD | EFI_ACPI_4_0_SLP_BUTTON |
EFI_ACPI_4_0_RESET_REG_SUP | EFI_ACPI_4_0_RTC_S4)
+#define IAPC_BOOT_ARCH ( EFI_ACPI_4_0_VGA_NOT_PRESENT | EFI_ACPI_4_0_8042 |
EFI_ACPI_4_0_LEGACY_DEVICES)
+#define RESERVED 0x00
+
+#endif
Added: trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/AcpiTables.inf
===================================================================
--- trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/AcpiTables.inf
(rev 0)
+++ trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/AcpiTables.inf
2015-01-12 09:37:20 UTC (rev 16599)
@@ -0,0 +1,44 @@
+## @file
+# Component description file for PlatformAcpiTable module.
+#
+# Build acpi table data required by system boot.
+# All .asi files tagged with "ToolCode="DUMMY"" in following file list are
device description and are included
+# by top level ASL file which will be dealed with by asl.exe application.
+#
+# Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
+#
+# This program and the accompanying materials are licensed and made available
under
+# the terms and conditions of the BSD License that accompanies this
distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#
+##
+
+[defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = AcpiTables
+ FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+ EDK_RELEASE_VERSION = 0x00020000
+ EFI_SPECIFICATION_VERSION = 0x00020000
+
+[sources.common]
+ DSDT.ASL
+ Facs/Facs.aslc
+ Facp/Facp.aslc
+ Madt/Madt30.aslc
+ Mcfg/Mcfg.aslc
+ Hpet/Hpet.aslc
+ Lpit/Lpit.aslc
+
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Vlv2TbltDevicePkg/PlatformPkg.dec
+ Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
Added: trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/CPU.asl
===================================================================
--- trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/CPU.asl
(rev 0)
+++ trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/CPU.asl 2015-01-12
09:37:20 UTC (rev 16599)
@@ -0,0 +1,55 @@
+/**************************************************************************;
+;* *;
+;* *;
+;* Intel Corporation - ACPI Reference Code for the Baytrail *;
+;* Family of Customer Reference Boards. *;
+;* *;
+;* *;
+;* Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved *;
+;
+; This program and the accompanying materials are licensed and made available
under
+; the terms and conditions of the BSD License that accompanies this
distribution.
+; The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;* *;
+;* *;
+;**************************************************************************/
+
+
+
+// NOTE: The _PDC Implementation is out of the scope of this
+// reference code. Please see the latest Hyper-Threading Technology
+// Reference Code for complete implementation details.
+
+Scope(\_PR)
+{
+ Processor(CPU0, // Unique name for Processor 0.
+ 1, // Unique ID for Processor 0.
+ 0x00, // CPU0 ACPI P_BLK address = ACPIBASE + 10h.
+ 0) // CPU0 P_BLK length = 6 bytes.
+ {}
+
+ Processor(CPU1, // Unique name for Processor 1.
+ 2, // Unique ID for Processor 1.
+ 0x00,
+ 0) // CPU1 P_BLK length = 6 bytes.
+ {}
+
+ Processor(CPU2, // Unique name for Processor 2.
+ 3, // Unique ID for Processor 2.
+ 0x00,
+ 0) // CPU2 P_BLK length = 6 bytes.
+ {}
+
+ Processor(CPU3, // Unique name for Processor 3.
+ 4, // Unique ID for Processor 3.
+ 0x00,
+ 0) // CPU3 P_BLK length = 6 bytes.
+ {}
+} // End _PR
+
+
Added: trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/DSDT.ASL
===================================================================
--- trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/DSDT.ASL
(rev 0)
+++ trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/DSDT.ASL 2015-01-12
09:37:20 UTC (rev 16599)
@@ -0,0 +1,81 @@
+/**************************************************************************;
+;* *;
+;* *;
+;* Intel Corporation - ACPI Reference Code for the Sandy Bridge *;
+;* Family of Customer Reference Boards. *;
+;* *;
+;* *;
+;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *;
+;
+; This program and the accompanying materials are licensed and made available
under
+; the terms and conditions of the BSD License that accompanies this
distribution.
+; The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;* *;
+;* *;
+;**************************************************************************/
+
+DefinitionBlock (
+ "DSDT.aml",
+ "DSDT",
+ 0x02, // DSDT revision.
+ "OEMID", // OEM ID (6 byte string)
+ "VLV-SOC", // OEM table ID (8 byte string)
+ 0x0 // OEM version of DSDT table (4 byte Integer)
+)
+
+// BEGIN OF ASL SCOPE
+{
+ External(MDBG, MethodObj)
+
+ Method(ADBG, 1, Serialized)
+ {
+
+ If(CondRefOf(MDBG)) //check if SSDT is loaded
+ {
+ Return(MDBG(Arg0))
+ }
+
+ Return(0)
+ }
+
+
+// Miscellaneous services enabled in Project
+ include ("token.asl")
+ include ("GloblNvs.asl")
+ include ("PciTree.asl")
+ include ("Pch.asl")
+ include ("Vlv.asl")
+ include ("CPU.asl")
+ include ("Platform.asl")
+ include ("THERMAL.ASL")
+ include ("PCI_DRC.ASL")
+ include ("Video.asl")
+ include ("Gpe.asl")
+ include ("IoTVirtualDevice.asl")
+
+ // Sleep states supported by Chipset/Board.
+ // SSx - BIOS setup controlled enabled _Sx Sleep state status
+ // Values to be written to SLP_TYPE register are provided by SBACPI.SDL
(South Bridge ACPI ModulePart)
+
+ Name(\_S0, Package(4) {0x0,0x0,0,0}) // mandatory System state
+ Name(\_S1, Package(4) {0x1,0x0,0,0})
+ Name(\_S3, Package(4) {0x5,0x0,0,0})
+ Name(\_S4, Package(4) {0x6,0x0,0,0})
+ Name(\_S5, Package(4) {0x7,0x0,0,0}) // mandatory System state
+
+ Method(PTS, 1) // METHOD CALLED FROM _PTS PRIOR TO ENTER ANY SLEEP
STATE
+ {
+ If(Arg0) // entering any sleep state
+ {
+ }
+ }
+ Method(WAK, 1) // METHOD CALLED FROM _WAK RIGHT AFTER WAKE UP
+ {
+ }
+
+}// End of ASL File
Added: trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Facp/Facp.aslc
===================================================================
--- trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Facp/Facp.aslc
(rev 0)
+++ trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Facp/Facp.aslc
2015-01-12 09:37:20 UTC (rev 16599)
@@ -0,0 +1,194 @@
+/*++
+
+Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
+
+ This program and the accompanying materials are licensed and made available
under
+ the terms and conditions of the BSD License that accompanies this
distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+Module Name:
+
+ Facp.c
+
+
+Abstract: The fixed ACPI description Table (FADT) Structure
+
+
+--*/
+#ifdef ECP_FLAG
+#include "EDKIIGlueDxe.h"
+#else
+#include <PiDxe.h>
+#endif
+#include <IndustryStandard/Acpi50.h>
+#include "AcpiTablePlatform.h"
+
+EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE FACP = {
+ {
+ EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+ sizeof (EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE),
+ EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,
+ 0,
// to make sum of entire table == 0
+ EFI_ACPI_OEM_ID, // OEMID is a 6 bytes long field
+ EFI_ACPI_OEM_TABLE_ID, // OEM table identification(8 bytes long)
+ EFI_ACPI_OEM_REVISION, // OEM revision number
+ EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID
+ EFI_ACPI_CREATOR_REVISION // ASL compiler revision number
+ },
+ 0,
// Physical addesss of FACS
+ 0,
// Physical address of DSDT
+ INT_MODEL,
// System Interrupt Model (ignored in 2k and later, must be 0
for 98)
+ PM_PROFILE,
// Preferred PM Profile
+ SCI_INT_VECTOR,
// System vector of SCI interrupt
+ SMI_CMD_IO_PORT,
// Port address of SMI command port
+ ACPI_ENABLE,
// value to write to port smi_cmd to enable ACPI
+ ACPI_DISABLE,
// value to write to port smi_cmd to disable ACPI
+ S4BIOS_REQ,
// Value to write to SMI CMD port to enter the S4BIOS state
+ PSTATE_CNT, // PState control
+ PM1a_EVT_BLK,
// Port address of Power Mgt 1a Event Reg Blk
+ PM1b_EVT_BLK,
// Port address of Power Mgt 1b Event Reg Blk
+ PM1a_CNT_BLK,
// Port address of Power Mgt 1a Ctrl Reg Blk
+ PM1b_CNT_BLK,
// Port address of Power Mgt 1b Ctrl Reg Blk
+ PM2_CNT_BLK,
// Port address of Power Mgt 2 Ctrl Reg Blk
+ PM_TMR_BLK,
// Port address of Power Mgt Timer Ctrl Reg Blk
+ GPE0_BLK,
// Port addr of General Purpose Event 0 Reg Blk
+ GPE1_BLK,
// Port addr of General Purpose Event 1 Reg Blk
+ PM1_EVT_LEN,
// Byte Length of ports at pm1X_evt_blk
+ PM1_CNT_LEN,
// Byte Length of ports at pm1X_cnt_blk
+ PM2_CNT_LEN,
// Byte Length of ports at pm2_cnt_blk
+ PM_TM_LEN,
// Byte Length of ports at pm_tm_blk
+ GPE0_BLK_LEN,
// Byte Length of ports at gpe0_blk
+ GPE1_BLK_LEN,
// Byte Length of ports at gpe1_blk
+ GPE1_BASE,
// offset in gpe model where gpe1 events start
+ CST_CNT, // _CST support
+ P_LVL2_LAT,
// worst case HW latency to enter/exit C2 state
+ P_LVL3_LAT,
// worst case HW latency to enter/exit C3 state
+ FLUSH_SIZE,
// Size of area read to flush caches
+ FLUSH_STRIDE,
// Stride used in flushing caches
+ DUTY_OFFSET,
// bit location of duty cycle field in p_cnt reg
+ DUTY_WIDTH,
// bit width of duty cycle field in p_cnt reg
+ DAY_ALRM,
// index to day-of-month alarm in RTC CMOS RAM
+ MON_ALRM,
// index to month-of-year alarm in RTC CMOS RAM
+ CENTURY,
// index to century in RTC CMOS RAM
+ IAPC_BOOT_ARCH,
// IA-PCI Boot Architecture Flag
+ RESERVED,
// reserved
+ FLAG,
+ {
+ EFI_ACPI_5_0_SYSTEM_IO,
+ 8,
+ 0,
+ 0,
+ 0xCF9
+ },
+ 0x06, // Hardware reset value
+ 0, 0, 0, // Reserved
+ 0, // XFirmwareCtrl
+ 0, // XDsdt
+ //
+ // X_PM1a Event Register Block
+ //
+ EFI_ACPI_5_0_SYSTEM_IO,
+ 0x20,
+ 0x00,
+ EFI_ACPI_3_0_DWORD,
+ PM1a_EVT_BLK,
+
+ //
+ // X_PM1b Event Register Block
+ //
+ EFI_ACPI_5_0_SYSTEM_IO,
+ 0x00,
+ 0x00,
+ EFI_ACPI_RESERVED_BYTE,
+ PM1b_EVT_BLK,
+
+ //
+ // X_PM1a Control Register Block
+ //
+ EFI_ACPI_5_0_SYSTEM_IO,
+ 0x10,
+ 0x00,
+ EFI_ACPI_3_0_WORD,
+ PM1a_CNT_BLK,
+
+ //
+ // X_PM1b Control Register Block
+ //
+ EFI_ACPI_5_0_SYSTEM_IO,
+ 0x00,
+ 0x00,
+ EFI_ACPI_RESERVED_BYTE,
+ PM1b_CNT_BLK,
+
+ //
+ // X_PM2 Control Register Block
+ //
+ EFI_ACPI_5_0_SYSTEM_IO,
+ 0x08,
+ 0x00,
+ EFI_ACPI_3_0_BYTE,
+ PM2_CNT_BLK,
+
+ //
+ // X_PM Timer Control Register Block
+ //
+ EFI_ACPI_5_0_SYSTEM_IO,
+ 0x20,
+ 0x00,
+ EFI_ACPI_3_0_DWORD,
+ PM_TMR_BLK,
+
+ //
+ // X_General Purpose Event 0 Register Block
+ //
+ EFI_ACPI_5_0_SYSTEM_IO,
+ 0x80,
+ 0x00,
+ EFI_ACPI_RESERVED_BYTE,
+ GPE0_BLK,
+
+ //
+ // X_General Purpose Event 1 Register Block
+ //
+ EFI_ACPI_5_0_SYSTEM_IO,
+ 0x00,
+ 0x00,
+ EFI_ACPI_RESERVED_BYTE,
+ GPE1_BLK,
+
+ //
+ // Sleep Control Register Block
+ //
+ EFI_ACPI_5_0_SYSTEM_IO,
+ 0x08,
+ 0x00,
+ EFI_ACPI_RESERVED_BYTE,
+ 0,
+
+ //
+ // Sleep Status Register Block
+ //
+ EFI_ACPI_5_0_SYSTEM_IO,
+ 0x08,
+ 0x00,
+ EFI_ACPI_RESERVED_BYTE,
+ 0,
+};
+
+VOID*
+ReferenceAcpiTable (
+ VOID
+ )
+{
+ //
+ // Reference the table being generated to prevent the optimizer from
+ // removing the data structure from the executable
+ //
+ return (VOID*)&FACP;
+}
Added: trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Facs/Facs.aslc
===================================================================
--- trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Facs/Facs.aslc
(rev 0)
+++ trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Facs/Facs.aslc
2015-01-12 09:37:20 UTC (rev 16599)
@@ -0,0 +1,90 @@
+/*++
+
+Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
+
+ This program and the accompanying materials are licensed and made available
under
+ the terms and conditions of the BSD License that accompanies this
distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+Module Name:
+
+ Ea815acpiFACS.c
+
+
+Abstract:
+
+ This file contains the FACS structure definition.
+
+--*/
+
+//
+// Statements that include other files
+//
+#ifdef ECP_FLAG
+#include "EDKIIGlueDxe.h"
+#else
+#include <PiDxe.h>
+#endif
+#include <IndustryStandard/Acpi50.h>
+#include "AcpiTablePlatform.h"
+
+EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE FACS = {
+ EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE,
+ sizeof (EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE),
+
+ //
+ // Hardware Signature will be updated at runtime
+ //
+ 0x00000000, //HardwareSignature
+ 0x00000000, //FirmwareWakingVector
+ 0x00000000, //GlobalLock
+ 0x00000000, //Flags
+ 0x0000000000000000, //XFirmwareWakingVector
+ EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION,
+ EFI_ACPI_RESERVED_BYTE, //Reserved0[3]
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ 0x00000000, //OspmFlags
+ EFI_ACPI_RESERVED_BYTE, //Reserved1[24]
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE
+};
+
+VOID*
+ReferenceAcpiTable (
+ VOID
+ )
+{
+ //
+ // Reference the table being generated to prevent the optimizer from
+ // removing the data structure from the executable
+ //
+ return (VOID*)&FACS;
+}
Added: trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/GloblNvs.asl
===================================================================
--- trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/GloblNvs.asl
(rev 0)
+++ trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/GloblNvs.asl 2015-01-12
09:37:20 UTC (rev 16599)
@@ -0,0 +1,352 @@
+/**************************************************************************;
+;* *;
+;* *;
+;* Intel Corporation - ACPI Reference Code for the Baytrail *;
+;* Family of Customer Reference Boards. *;
+;* *;
+;* *;
+;* Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved *;
+;
+; This program and the accompanying materials are licensed and made available
under
+; the terms and conditions of the BSD License that accompanies this
distribution.
+; The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;* *;
+;* *;
+;**************************************************************************/
+
+
+
+// Define a Global region of ACPI NVS Region that may be used for any
+// type of implementation. The starting offset and size will be fixed
+// up by the System BIOS during POST. Note that the Size must be a word
+// in size to be fixed up correctly.
+
+OperationRegion(GNVS,SystemMemory,0xFFFF0000,0xAA55)
+Field(GNVS,AnyAcc,Lock,Preserve)
+{
+ Offset(0), // Miscellaneous Dynamic Registers:
+ OSYS, 16, // (00) Operating System
+ , 8, // (02)
+ , 8, // (03)
+ , 8, // (04)
+ , 8, // (05)
+ , 8, // (06)
+ , 8, // (07)
+ , 8, // (08)
+ , 8, // (09)
+ , 8, // (10)
+ P80D, 32, // (11) Port 80 Debug Port Value
+ LIDS, 8, // (15) Lid State (Lid Open = 1)
+ , 8, // (16)
+ , 8, // (17)
+ Offset(18), // Thermal Policy Registers:
+ , 8, // (18)
+ , 8, // (19)
+ ACTT, 8, // (20) Active Trip Point
+ PSVT, 8, // (21) Passive Trip Point
+ TC1V, 8, // (22) Passive Trip Point TC1 Value
+ TC2V, 8, // (23) Passive Trip Point TC2 Value
+ TSPV, 8, // (24) Passive Trip Point TSP Value
+ CRTT, 8, // (25) Critical Trip Point
+ DTSE, 8, // (26) Digital Thermal Sensor Enable
+ DTS1, 8, // (27) Digital Thermal Sensor 1 Reading
+ DTS2, 8, // (28) Digital Thermal Sensor 2 Reading
+ DTSF, 8, // (29) DTS SMI Function Call
+ Offset(30), // Battery Support Registers:
+ , 8, // (30)
+ , 8, // (31)
+ , 8, // (32)
+ , 8, // (33)
+ , 8, // (34)
+ , 8, // (35)
+ , 8, // (36)
+ Offset(40), // CPU Identification Registers:
+ APIC, 8, // (40) APIC Enabled by SBIOS (APIC Enabled = 1)
+ MPEN, 8, // (41) Number of Logical Processors if MP Enabled != 0
+ , 8, // (42)
+ , 8, // (43)
+ , 8, // (44)
+ , 32, // (45)
+ Offset(50), // SIO CMOS Configuration Registers:
+ , 8, // (50)
+ , 8, // (51)
+ , 8, // (52)
+ , 8, // (53)
+ , 8, // (54)
+ , 8, // (55)
+ , 8, // (56)
+ , 8, // (57)
+ , 8, // (58)
+ Offset(60), // Internal Graphics Registers:
+ , 8, // (60)
+ , 8, // (61)
+ CADL, 8, // (62) Current Attached Device List
+ , 8, // (63)
+ CSTE, 16, // (64) Current Display State
+ NSTE, 16, // (66) Next Display State
+ , 16, // (68)
+ NDID, 8, // (70) Number of Valid Device IDs
+ DID1, 32, // (71) Device ID 1
+ DID2, 32, // (75) Device ID 2
+ DID3, 32, // (79) Device ID 3
+ DID4, 32, // (83) Device ID 4
+ DID5, 32, // (87) Device ID 5
+ , 32, // (91)
+ , 8, // (95) Fifth byte of AKSV (mannufacturing mode)
+ Offset(103), // Backlight Control Registers:
+ , 8, // (103)
+ BRTL, 8, // (104) Brightness Level Percentage
+ Offset(105), // Ambiant Light Sensor Registers:
+ , 8, // (105)
+ , 8, // (106)
+ LLOW, 8, // (107) LUX Low Value
+ , 8, // (108)
+ Offset(110), // EMA Registers:
+ , 8, // (110)
+ , 16, // (111)
+ , 16, // (113)
+ Offset(116), // MEF Registers:
+ , 8, // (116) MEF Enable
+ Offset(117), // PCIe Dock:
+ , 8, // (117)
+ Offset(120), // TPM Registers:
+ , 8, // (120)
+ , 8, // (121)
+ , 8, // (122)
+ , 8, // (123)
+ , 32, // (124)
+ , 8, // (125)
+ , 8, // (129)
+ Offset(130), //
+ , 56, // (130)
+ , 56, // (137)
+ , 8, // (144)
+ , 56, // (145)
+ Offset(170), // IGD OpRegion/Software SCI base address
+ ASLB, 32, // (170) IGD OpRegion base address
+ Offset(174), // IGD OpRegion/Software SCI shared data
+ IBTT, 8, // (174) IGD Boot Display Device
+ IPAT, 8, // (175) IGD Panel Type CMOs option
+ ITVF, 8, // (176) IGD TV Format CMOS option
+ ITVM, 8, // (177) IGD TV Minor Format CMOS option
+ IPSC, 8, // (178) IGD Panel Scaling
+ IBLC, 8, // (179) IGD BLC Configuration
+ IBIA, 8, // (180) IGD BIA Configuration
+ ISSC, 8, // (181) IGD SSC Configuration
+ I409, 8, // (182) IGD 0409 Modified Settings Flag
+ I509, 8, // (183) IGD 0509 Modified Settings Flag
+ I609, 8, // (184) IGD 0609 Modified Settings Flag
+ I709, 8, // (185) IGD 0709 Modified Settings Flag
+ IDMM, 8, // (186) IGD DVMT Mode
+ IDMS, 8, // (187) IGD DVMT Memory Size
+ IF1E, 8, // (188) IGD Function 1 Enable
+ HVCO, 8, // (189) HPLL VCO
+ NXD1, 32, // (190) Next state DID1 for _DGS
+ NXD2, 32, // (194) Next state DID2 for _DGS
+ NXD3, 32, // (198) Next state DID3 for _DGS
+ NXD4, 32, // (202) Next state DID4 for _DGS
+ NXD5, 32, // (206) Next state DID5 for _DGS
+ NXD6, 32, // (210) Next state DID6 for _DGS
+ NXD7, 32, // (214) Next state DID7 for _DGS
+ NXD8, 32, // (218) Next state DID8 for _DGS
+ GSMI, 8, // (222) GMCH SMI/SCI mode (0=SCI)
+ PAVP, 8, // (223) IGD PAVP data
+ Offset(225),
+ OSCC, 8, // (225) PCIE OSC Control
+ NEXP, 8, // (226) Native PCIE Setup Value
+ Offset(235), // Global Variables
+ DSEN, 8, // (235) _DOS Display Support Flag.
+ ECON, 8, // (236) Embedded Controller Availability Flag.
+ GPIC, 8, // (237) Global IOAPIC/8259 Interrupt Mode Flag.
+ CTYP, 8, // (238) Global Cooling Type Flag.
+ L01C, 8, // (239) Global L01 Counter.
+ VFN0, 8, // (240) Virtual Fan0 Status.
+ VFN1, 8, // (241) Virtual Fan1 Status.
+ Offset(256),
+ NVGA, 32, // (256) NVIG opregion address
+ NVHA, 32, // (260) NVHM opregion address
+ AMDA, 32, // (264) AMDA opregion address
+ DID6, 32, // (268) Device ID 6
+ DID7, 32, // (272) Device ID 7
+ DID8, 32, // (276) Device ID 8
+ Offset(332),
+ USEL, 8, // (332) UART Selection
+ PU1E, 8, // (333) PCU UART 1 Enabled
+ PU2E, 8, // (334) PCU UART 2 Enabled
+
+ LPE0, 32, // (335) LPE Bar0
+ LPE1, 32, // (339) LPE Bar1
+ LPE2, 32, // (343) LPE Bar2
+
+ Offset(347),
+ , 8, // (347)
+ , 8, // (348)
+ PFLV, 8, // (349) Platform Flavor
+
+ Offset(351),
+ ICNF, 8, // (351) ISCT / AOAC Configuration
+ XHCI, 8, // (352) xHCI controller mode
+ PMEN, 8, // (353) PMIC enable/disable
+
+ LPEE, 8, // (354) LPE enable/disable
+ ISPA, 32, // (355) ISP Base Addr
+ ISPD, 8, // (359) ISP Device Selection 0: Disabled; 1: PCI Device 2;
2: PCI Device 3
+
+ offset(360), // ((4+8+6)*4+2)*4=296
+ //
+ // Lpss controllers
+ //
+ PCIB, 32,
+ PCIT, 32,
+ D10A, 32, //DMA1
+ D10L, 32,
+ D11A, 32,
+ D11L, 32,
+ P10A, 32, // PWM1
+ P10L, 32,
+ P11A, 32,
+ P11L, 32,
+ P20A, 32, // PWM2
+ P20L, 32,
+ P21A, 32,
+ P21L, 32,
+ U10A, 32, // UART1
+ U10L, 32,
+ U11A, 32,
+ U11L, 32,
+ U20A, 32, // UART2
+ U20L, 32,
+ U21A, 32,
+ U21L, 32,
+ SP0A, 32, // SPI
+ SP0L, 32,
+ SP1A, 32,
+ SP1L, 32,
+
+ D20A, 32, //DMA2
+ D20L, 32,
+ D21A, 32,
+ D21L, 32,
+ I10A, 32, // I2C1
+ I10L, 32,
+ I11A, 32,
+ I11L, 32,
+ I20A, 32, // I2C2
+ I20L, 32,
+ I21A, 32,
+ I21L, 32,
+ I30A, 32, // I2C3
+ I30L, 32,
+ I31A, 32,
+ I31L, 32,
+ I40A, 32, // I2C4
+ I40L, 32,
+ I41A, 32,
+ I41L, 32,
+ I50A, 32, // I2C5
+ I50L, 32,
+ I51A, 32,
+ I51L, 32,
+ I60A, 32, // I2C6
+ I60L, 32,
+ I61A, 32,
+ I61L, 32,
+ I70A, 32, // I2C7
+ I70L, 32,
+ I71A, 32,
+ I71L, 32,
+ //
+ // Scc controllers
+ //
+ eM0A, 32, // EMMC
+ eM0L, 32,
+ eM1A, 32,
+ eM1L, 32,
+ SI0A, 32, // SDIO
+ SI0L, 32,
+ SI1A, 32,
+ SI1L, 32,
+ SD0A, 32, // SDCard
+ SD0L, 32,
+ SD1A, 32,
+ SD1L, 32,
+ MH0A, 32, //
+ MH0L, 32,
+ MH1A, 32,
+ MH1L, 32,
+
+ offset(656),
+ SDRM, 8,
+ offset(657),
+ HLPS, 8, //(657) Hide Devices
+ offset(658),
+ OSEL, 8, //(658) OS Seletion - Windows/Android
+
+ offset(659), // VLV1 DPTF
+ SDP1, 8, //(659) An enumerated value corresponding to SKU
+ DPTE, 8, //(660) DPTF Enable
+ THM0, 8, //(661) System Thermal 0
+ THM1, 8, //(662) System Thermal 1
+ THM2, 8, //(663) System Thermal 2
+ THM3, 8, //(664) System Thermal 3
+ THM4, 8, //(665) System Thermal 3
+ CHGR, 8, //(666) DPTF Changer Device
+ DDSP, 8, //(667) DPTF Display Device
+ DSOC, 8, //(668) DPTF SoC device
+ DPSR, 8, //(669) DPTF Processor device
+ DPCT, 32, //(670) DPTF Processor participant critical temperature
+ DPPT, 32, //(674) DPTF Processor participant passive temperature
+ DGC0, 32, //(678) DPTF Generic sensor0 participant critical
temperature
+ DGP0, 32, //(682) DPTF Generic sensor0 participant passive
temperature
+ DGC1, 32, //(686) DPTF Generic sensor1 participant critical
temperature
+ DGP1, 32, //(690) DPTF Generic sensor1 participant passive
temperature
+ DGC2, 32, //(694) DPTF Generic sensor2 participant critical
temperature
+ DGP2, 32, //(698) DPTF Generic sensor2 participant passive
temperature
+ DGC3, 32, //(702) DPTF Generic sensor3 participant critical
temperature
+ DGP3, 32, //(706) DPTF Generic sensor3 participant passive
temperature
+ DGC4, 32, //(710)DPTF Generic sensor3 participant critical
temperature
+ DGP4, 32, //(714)DPTF Generic sensor3 participant passive temperature
+ DLPM, 8, //(718) DPTF Current low power mode setting
+ DSC0, 32, //(719) DPTF Critical threshold0 for SCU
+ DSC1, 32, //(723) DPTF Critical threshold1 for SCU
+ DSC2, 32, //(727) DPTF Critical threshold2 for SCU
+ DSC3, 32, //(731) DPTF Critical threshold3 for SCU
+ DSC4, 32, //(735) DPTF Critical threshold3 for SCU
+ DDBG, 8, //(739) DPTF Super Debug option. 0 - Disabled, 1 - Enabled
+ LPOE, 32, //(740) DPTF LPO Enable
+ LPPS, 32, //(744) P-State start index
+ LPST, 32, //(748) Step size
+ LPPC, 32, //(752) Power control setting
+ LPPF, 32, //(756) Performance control setting
+ DPME, 8, //(760) DPTF DPPM enable/disable
+ BCSL, 8, //(761) Battery charging solution 0-CLV 1-ULPMC
+ NFCS, 8, //(762) NFCx Select 1: NFC1 2:NFC2
+ PCIM, 8, //(763) EMMC device 0-ACPI mode, 1-PCI mode
+ TPMA, 32, //(764)
+ TPML, 32, //(768)
+ ITSA, 8, //(772) I2C Touch Screen Address
+ S0IX, 8, //(773) S0ix status
+ SDMD, 8, //(774) SDIO Mode
+ EMVR, 8, //(775) eMMC controller version
+ BMBD, 32, //(776) BM Bound
+ FSAS, 8, //(780) FSA Status
+ BDID, 8, //(781) Board ID
+ FBID, 8, //(782) FAB ID
+ OTGM, 8, //(783) OTG mode
+ STEP, 8, //(784) Stepping ID
+ WITT, 8, //(785) Enable Test Device connected to I2C for WHCK test.
+ SOCS, 8, //(786) provide the SoC stepping infomation
+ AMTE, 8, //(787) Ambient Trip point change
+ UTS, 8, //(788) Enable Test Device connected to URT for WHCK test.
+ SCPE, 8, //(789) Allow higher performance on AC/USB - Enable/Disable
+ Offset(792),
+ EDPV, 8, //(792) Check for eDP display device
+ DIDX, 32, //(793) Device ID for eDP device
+ IOT, 8, //(794) MinnowBoard Max JP1 is configured for MSFT IOT
project.
+}
+
Added: trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Gpe.asl
===================================================================
--- trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Gpe.asl
(rev 0)
+++ trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Gpe.asl 2015-01-12
09:37:20 UTC (rev 16599)
@@ -0,0 +1,105 @@
+/**************************************************************************;
+;* *;
+;* *;
+;* Intel Corporation - ACPI Reference Code for the Baytrail *;
+;* Family of Customer Reference Boards. *;
+;* *;
+;* *;
+;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *;
+;
+; This program and the accompanying materials are licensed and made available
under
+; the terms and conditions of the BSD License that accompanies this
distribution.
+; The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;* *;
+;* *;
+;**************************************************************************/
+
+
+// General Purpose Events. This Scope handles the Run-time and
+// Wake-time SCIs. The specific method called will be determined by
+// the _Lxx value, where xx equals the bit location in the General
+// Purpose Event register(s).
+
+Scope(\_GPE)
+{
+ //
+ // Software GPE caused the event.
+ //
+ Method(_L02)
+ {
+ // Clear GPE status bit.
+ Store(0,GPEC)
+ //
+ // Handle DTS Thermal Events.
+ //
+ External(DTSE, IntObj)
+ If(CondRefOf(DTSE))
+ {
+ If(LGreaterEqual(DTSE, 0x01))
+ {
+ Notify(\_TZ.TZ01,0x80)
+ }
+ }
+ }
+
+ //
+ // PUNIT SCI event.
+ //
+ Method(_L04)
+ {
+ // Clear the PUNIT Status Bit.
+ Store(1, PSCI)
+ }
+
+
+ //
+ // IGD OpRegion SCI event (see IGD OpRegion/Software SCI BIOS SPEC).
+ //
+ Method(_L05)
+ {
+ If(LAnd(\_SB.PCI0.GFX0.GSSE, LNot(GSMI))) // Graphics software SCI event?
+ {
+ \_SB.PCI0.GFX0.GSCI() // Handle the SWSCI
+ }
+ }
+
+ //
+ // This PME event (PCH's GPE #13) is received when any PCH internal device
with PCI Power Management capabilities
+ // on bus 0 asserts the equivalent of the PME# signal.
+ //
+ Method(_L0D, 0)
+ {
+ If(LAnd(\_SB.PCI0.EHC1.PMEE, \_SB.PCI0.EHC1.PMES))
+ {
+ If(LNotEqual(OSEL, 1))
+ {
+ Store(1, \_SB.PCI0.EHC1.PMES) //Clear PME status
+ Store(0, \_SB.PCI0.EHC1.PMEE) //Disable PME
+ }
+ Notify(\_SB.PCI0.EHC1, 0x02)
+ }
+ If(LAnd(\_SB.PCI0.XHC1.PMEE, \_SB.PCI0.XHC1.PMES))
+ {
+ If(LNotEqual(OSEL, 1))
+ {
+ Store(1, \_SB.PCI0.XHC1.PMES) //Clear PME status
+ Store(0, \_SB.PCI0.XHC1.PMEE) //Disable PME
+ }
+ Notify(\_SB.PCI0.XHC1, 0x02)
+ }
+ If(LAnd(\_SB.PCI0.HDEF.PMEE, \_SB.PCI0.HDEF.PMES))
+ {
+ If(LNotEqual(OSEL, 1))
+ {
+ Store(1, \_SB.PCI0.HDEF.PMES) //Clear PME status
+ Store(0, \_SB.PCI0.HDEF.PMEE) //Disable PME
+ }
+ Notify(\_SB.PCI0.HDEF, 0x02)
+ }
+ }
+}
Added: trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/HOST_BUS.ASL
===================================================================
--- trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/HOST_BUS.ASL
(rev 0)
+++ trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/HOST_BUS.ASL 2015-01-12
09:37:20 UTC (rev 16599)
@@ -0,0 +1,353 @@
+/*++
+
+Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
+
+ This program and the accompanying materials are licensed and made available
under
+ the terms and conditions of the BSD License that accompanies this
distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+Module Name:
+
+ HOST_BUS.ASL
+
+Abstract:
+
+ Baytrail PCI configuration space definition.
+
+---*/
+Device(VLVC)
+{
+ Name(_ADR, 0x00000000) // Device 0, Function 0
+
+ // Define various MCH Controller PCI Configuration Space
+ // registers which will be used to dynamically produce all
+ // resources in the Host Bus _CRS.
+ OperationRegion(HBUS, PCI_Config, 0x00, 0xFF)
+ Field(HBUS, DWordAcc, NoLock, Preserve)
+ {
+ Offset(0xD0),
+ SMCR, 32, // VLV Message Control Register (0xD0)
+ Offset(0xD4),
+ SMDR, 32, // VLV Message Data Register (0xD4)
+ Offset(0xD8),
+ MCRX, 32, // VLV Message Control Register Extension (0xD8)
+ }
+
+ // Define a method to read a 32-bit register on the VLV Message bus.
+ // Arg0 = Port
+ // Arg1 = Register
+ //
+ // Returns 32-bit register value
+
+ Method(RMBR, 2, Serialized)
+ {
+
+ // Initiate regsiter read message on VLV Message Bus MCR
+
+ Or(ShiftLeft(Arg0, 16), ShiftLeft(Arg1, 8), Local0)
+ Or(0x100000F0, Local0, SMCR)
+
+ // Read register value from Message Data Register
+
+ Return(SMDR)
+ }
+
+
+ // Define a method to write a 32-bit register on the VLV Message bus MDR.
+ // Arg0 = Port
+ // Arg1 = Register
+ // Arg2 = 32-bit value
+
+ Method(WMBR, 3, Serialized)
+ {
+
+ // Write register value to Message Data Register
+
+ Store(Arg2, SMDR)
+
+ // Initiate register write message on VLV Message Bus
+
+ Or(ShiftLeft(Arg0, 16), ShiftLeft(Arg1, 8), Local0)
+ Or(0x110000F0, Local0, SMCR)
+ }
+}
+
+//
+// BUS, I/O, and MMIO resources
+//
+Method(_CRS,0,Serialized)
+{
+ //Update ISP0 reserved memory
+ CreateDwordField(RES0, ^ISP0._MIN,ISMN)
+ CreateDwordField(RES0, ^ISP0._MAX,ISMX)
+ CreateDwordField(RES0, ^ISP0._LEN,ISLN)
+ If (LEqual(ISPD,1))
+ {
+ Store (ISPA, ISMN)
+ Add (ISMN, ISLN, ISMX)
+ Subtract(ISMX, 1, ISMX)
+ } Else
+ {
+ Store (0, ISMN)
+ Store (0, ISMX)
+ Store (0, ISLN)
+ }
+
+ //PCI MMIO SPACE
+ CreateDwordField(RES0, ^PM01._MIN,M1MN)
+ CreateDwordField(RES0, ^PM01._MAX,M1MX)
+ CreateDwordField(RES0, ^PM01._LEN,M1LN)
+
+ //Get dBMBOUND Base
+ And(BMBD, 0xFF000000, M1MN)
+
+ //Get ECBASE
+ Store(PCIT, M1MX)
+ Add(Subtract(M1MX, M1MN), 1, M1LN)
+ Subtract(M1MX, 1, M1MX)
+
+ // Create pointers to Gfx Stolen Memory Sizing values.
+ CreateDwordField(RES0, ^STOM._MIN,GSMN)
+ CreateDwordField(RES0, ^STOM._MAX,GSMX)
+ CreateDwordField(RES0, ^STOM._LEN,GSLN)
+
+ If (LNotEqual (\_SB.PCI0.GFX0.GSTM, 0xFFFFFFFF))
+ {
+ Store(0x00, GSMN) //Read the Stolen memory base from B0:D2:F0:R5C
+ } else
+ {
+ Store(\_SB.PCI0.GFX0.GSTM, GSMN) //Read the Stolen memory base from
B0:D2:F0:R5C
+ }
+ If (LNotEqual (\_SB.PCI0.GFX0.GUMA, 0xFFFFFFFF))
+ {
+ Store(0x00, GSLN) //Read the Stolen memory base from B0:D2:F0:R5C
+ } else
+ {
+ ShiftLeft(\_SB.PCI0.GFX0.GUMA, 25, GSLN) //Read Stolen memory base form
B0:D2:F0:R50
+ }
+ Add(GSMN, GSLN, GSMX) //Store the Stolen Memory Size
+ Subtract(GSMX, 1, GSMX)
+
+ Return(RES0)
+}
+
+Name( RES0,ResourceTemplate()
+{
+ WORDBusNumber ( // Bus number resource (0); the bridge produces bus
numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity
+ 0x0000, // Min
+ 0x00FF, // Max
+ 0x0000, // Translation
+ 0x0100 // Range Length = Max-Min+1
+ )
+
+ IO (Decode16, 0x70, 0x77, 0x01, 0x08) //Consumed resource
(0xCF8-0xCFF)
+ IO (Decode16, 0xCF8, 0xCF8, 0x01, 0x08) //Consumed resource
(0xCF8-0xCFF)
+
+ WORDIO ( // Consumed-and-produced resource (all I/O below
CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity
+ 0x0000, // Min
+ 0x006F, // Max
+ 0x0000, // Translation
+ 0x0070 // Range Length
+ )
+
+ WORDIO ( // Consumed-and-produced resource
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity
+ 0x0078, // Min
+ 0x0CF7, // Max
+ 0x0000, // Translation
+ 0x0C80 // Range Length
+ )
+
+ WORDIO ( // Consumed-and-produced resource (all I/O above
CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity
+ 0x0D00, // Min
+ 0xFFFF, // Max
+ 0x0000, // Translation
+ 0xF300 // Range Length
+ )
+
+ DWORDMEMORY ( // Descriptor for legacy VGA video RAM
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ 0x000A0000, // Min
+ 0x000BFFFF, // Max
+ 0x00000000, // Translation
+ 0x00020000 // Range Length
+ )
+
+ DWORDMEMORY ( // Descriptor for legacy OptionRom
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ 0x000C0000, // Min
+ 0x000DFFFF, // Max
+ 0x00000000, // Translation
+ 0x00020000 // Range Length
+ )
+
+ DWORDMEMORY ( // Descriptor for BIOS Area
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ 0x000E0000, // Min
+ 0x000FFFFF, // Max
+ 0x00000000, // Translation
+ 0x00020000 // Range Length
+ )
+
+ DWORDMEMORY ( // Descriptor for ISP0 reserved Mem
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ 0x7A000000, // Min
+ 0x7A3FFFFF, // Max
+ 0x00000000, // Translation
+ 0x00400000 // Range Length
+ ,,,
+ ISP0
+ )
+
+ DWORDMEMORY ( // Descriptor for VGA Stolen Mem
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ 0x7C000000, // Min
+ 0x7FFFFFFF, // Max
+ 0x00000000, // Translation
+ 0x04000000 // Range Length
+ ,,,
+ STOM
+ )
+
+ DWORDMEMORY ( // Descriptor for PCI MMIO
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ 0x80000000, // Min
+ 0xDFFFFFFF, // Max
+ 0x00000000, // Translation
+ 0x60000000 // Range Length
+ ,,,
+ PM01
+ )
+})
+
+//Name(GUID,UUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))
+Name(GUID,Buffer()
+{
+ 0x5b, 0x4d, 0xdb, 0x33,
+ 0xf7, 0x1f,
+ 0x1c, 0x40,
+ 0x96, 0x57,
+ 0x74, 0x41, 0xc0, 0x3d, 0xd7, 0x66
+})
+
+
+Name(SUPP,0) // PCI _OSC Support Field value
+Name(CTRL,0) // PCI _OSC Control Field value
+
+Method(_OSC,4,Serialized)
+{
+ // Check for proper UUID
+ // Save the capabilities buffer
+ Store(Arg3,Local0)
+
+ // Create DWord-adressable fields from the Capabilties Buffer
+ CreateDWordField(Local0,0,CDW1)
+ CreateDWordField(Local0,4,CDW2)
+ CreateDWordField(Local0,8,CDW3)
+
+ // Check for proper UUID
+ If(LAnd(LEqual(Arg0,GUID),NEXP))
+ {
+ // Save Capabilities DWord2 & 3
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ If(Not(And(CDW1,1))) // Query flag clear?
+ {
+ // Disable GPEs for features granted native control.
+ If(And(CTRL,0x02))
+ {
+ NHPG()
+ }
+ If(And(CTRL,0x04)) // PME control granted?
+ {
+ NPME()
+ }
+ }
+
+ If(LNotEqual(Arg1,One))
+ {
+ // Unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL))
+ {
+ // Capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ // Update DWORD3 in the buffer
+ And(CTRL,0xfe,CTRL)
+ Store(CTRL,CDW3)
+ Store(CTRL,OSCC)
+ Return(Local0)
+ } Else
+ {
+ Or(CDW1,4,CDW1) // Unrecognized UUID
+ Return(Local0)
+ }
+} // End _OSC
Added: trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Hpet/Hpet.aslc
===================================================================
--- trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Hpet/Hpet.aslc
(rev 0)
+++ trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Hpet/Hpet.aslc
2015-01-12 09:37:20 UTC (rev 16599)
@@ -0,0 +1,69 @@
+/*++
+
+Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
+
+ This program and the accompanying materials are licensed and made available
under
+ the terms and conditions of the BSD License that accompanies this
distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+Module Name:
+
+ Hpet.c
+
+Abstract:
+
+ This file contains a structure definition for the ACPI HPET Table.
+--*/
+
+//
+// Statements that include other files
+//
+#ifdef ECP_FLAG
+#include <Tiano.h>
+#endif
+#include <Hpet.h>
+#include "AcpiTablePlatform.h"
+
+// Hpet Table
+EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER HPET = {
+ {
+ EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE,
+ sizeof (EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER),
+ EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_REVISION,
+ 0, // to make sum of entire table == 0
+ EFI_ACPI_OEM_ID, // OEMID is a 6 bytes long field
+ EFI_ACPI_OEM_TABLE_ID, // OEM table identification(8 bytes long)
+ EFI_ACPI_OEM_REVISION, // OEM revision
+ EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID
+ EFI_ACPI_CREATOR_REVISION // ASL compiler revision number
+ },
+ 0x0, // EventTimerBlockId
+ {
+ 0x00, // Address_Space_ID = System Memory
+ 0x40, // Register_Bit_Width = 32 bits, mentioned about
write failures when in 64bit in SCU HAS
+ 0x00, // Register_Bit_offset
+ 0x00, // Dword access
+ HPET_BASE_ADDRESS, // Base addresse of HPET
+ },
+ 0x0, // Only HPET's _UID in Namespace
+ MAIN_COUNTER_MIN_PERIODIC_CLOCK_TICKS,
+ 0x0
+};
+
+VOID*
+ReferenceAcpiTable (
+ VOID
+ )
+{
+ //
+ // Reference the table being generated to prevent the optimizer from
+ // removing the data structure from the executable
+ //
+ return (VOID*)&HPET;
+}
Added: trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/INTELGFX.ASL
===================================================================
--- trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/INTELGFX.ASL
(rev 0)
+++ trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/INTELGFX.ASL 2015-01-12
09:37:20 UTC (rev 16599)
@@ -0,0 +1,885 @@
+/*++
+
+Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
+
+ This program and the accompanying materials are licensed and made available
under
+ the terms and conditions of the BSD License that accompanies this
distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+Module Name:
+
+ INTELGFX.ASL
+
+Abstract:
+
+ IGD OpRegion/Software ACPI Reference Code for the Baytrail Family.
+
+--*/
+
+// Enable/Disable Output Switching. In WIN2K/WINXP, _DOS = 0 will
+// get called during initialization to prepare for an ACPI Display
+// Switch Event. During an ACPI Display Switch, the OS will call
+// _DOS = 2 immediately after a Notify=0x80 to temporarily disable
+// all Display Switching. After ACPI Display Switching is complete,
+// the OS will call _DOS = 0 to re-enable ACPI Display Switching.
+
+Method(_DOS,1)
+{
+ // Store Display Switching and LCD brightness BIOS control bit
+ Store(And(Arg0,7),DSEN)
+}
+
+// Enumerate the Display Environment. This method will return
+// valid addresses for all display device encoders present in the
+// system. The Miniport Driver will reject the addresses for every
+// encoder that does not have an attached display device. After
+// enumeration is complete, the OS will call the _DGS methods
+// during a display switch only for the addresses accepted by the
+// Miniport Driver. For hot-insertion and removal of display
+// devices, a re-enumeration notification will be required so the
+// address of the newly present display device will be accepted by
+// the Miniport Driver.
+
+Method(_DOD, 0, Serialized)
+{
+ Store(0, NDID)
+ If(LNotEqual(DIDL, Zero))
+ {
+ Store(SDDL(DIDL),DID1)
+ }
+ If(LNotEqual(DDL2, Zero))
+ {
+ Store(SDDL(DDL2),DID2)
+ }
+ If(LNotEqual(DDL3, Zero))
+ {
+ Store(SDDL(DDL3),DID3)
+ }
+ If(LNotEqual(DDL4, Zero))
+ {
+ Store(SDDL(DDL4),DID4)
+ }
+ If(LNotEqual(DDL5, Zero))
+ {
+ Store(SDDL(DDL5),DID5)
+ }
+
+ // TODO - This level of flexibility is not needed for a true
+ // OEM design. Simply determine the greatest number of
+ // encoders the platform will suppport then remove all
+ // return packages beyond that value. Note that for
+ // current silicon, the maximum number of encoders
+ // possible is 5.
+
+ If(LEqual(NDID,1))
+ {
+ If (LNOTEqual (ISPD, 0))
+ {
+ Name(TMP0,Package() {0xFFFFFFFF,0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMP0,0))
+ //Add ISP device to GFX0
+ Store(0x00020F38, Index(TMP0,1))
+ Return(TMP0)
+ } Else
+ {
+ Name(TMP1,Package() {0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMP1,0))
+ Return(TMP1)
+ }
+ }
+
+ If(LEqual(NDID,2))
+ {
+ If (LNOTEqual (ISPD, 0))
+ {
+ Name(TMP2,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMP2,0))
+ Store(Or(0x10000,DID2),Index(TMP2,1))
+ //Add ISP device to GFX0
+ Store(0x00020F38, Index(TMP2,2))
+ Return(TMP2)
+ } Else
+ {
+ Name(TMP3,Package() {0xFFFFFFFF, 0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMP3,0))
+ Store(Or(0x10000,DID2),Index(TMP3,1))
+ Return(TMP3)
+ }
+ }
+
+ If(LEqual(NDID,3))
+ {
+ If (LNOTEqual (ISPD, 0))
+ {
+ Name(TMP4,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMP4,0))
+ Store(Or(0x10000,DID2),Index(TMP4,1))
+ Store(Or(0x10000,DID3),Index(TMP4,2))
+ //Add ISP device to GFX0
+ Store(0x00020F38, Index(TMP4,3))
+ Return(TMP4)
+ } Else
+ {
+ Name(TMP5,Package() {0xFFFFFFFF, 0xFFFFFFFF,0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMP5,0))
+ Store(Or(0x10000,DID2),Index(TMP5,1))
+ Store(Or(0x10000,DID3),Index(TMP5,2))
+ Return(TMP5)
+ }
+ }
+
+ If(LEqual(NDID,4))
+ {
+ If (LNOTEqual (ISPD, 0))
+ {
+ Name(TMP6,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMP6,0))
+ Store(Or(0x10000,DID2),Index(TMP6,1))
+ Store(Or(0x10000,DID3),Index(TMP6,2))
+ Store(Or(0x10000,DID4),Index(TMP6,3))
+ //Add ISP device to GFX0
+ Store(0x00020F38, Index(TMP6,4))
+ Return(TMP6)
+ } Else
+ {
+ Name(TMP7,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMP7,0))
+ Store(Or(0x10000,DID2),Index(TMP7,1))
+ Store(Or(0x10000,DID3),Index(TMP7,2))
+ Store(Or(0x10000,DID4),Index(TMP7,3))
+ Return(TMP7)
+ }
+ }
+
+ If(LGreater(NDID,4))
+ {
+ If (LNOTEqual (ISPD, 0))
+ {
+ Name(TMP8,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMP8,0))
+ Store(Or(0x10000,DID2),Index(TMP8,1))
+ Store(Or(0x10000,DID3),Index(TMP8,2))
+ Store(Or(0x10000,DID4),Index(TMP8,3))
+ Store(Or(0x10000,DID5),Index(TMP8,4))
+ //Add ISP device to GFX0
+ Store(0x00020F38, Index(TMP8,5))
+ Return(TMP8)
+ } Else
+ {
+ Name(TMP9,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMP9,0))
+ Store(Or(0x10000,DID2),Index(TMP9,1))
+ Store(Or(0x10000,DID3),Index(TMP9,2))
+ Store(Or(0x10000,DID4),Index(TMP9,3))
+ Store(Or(0x10000,DID5),Index(TMP9,4))
+ Return(TMP9)
+ }
+ }
+
+ // If nothing else, return Unknown LFP.
+ // (Prevents compiler warning.)
+
+ //Add ISP device to GFX0
+ If (LNOTEqual (ISPD, 0))
+ {
+ Return(Package() {0x00000400, 0x00020F38})
+ } Else
+ {
+ Return(Package() {0x00000400})
+ }
+}
+
+Device(DD01)
+{
+
+ // Return Unique ID.
+
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(And(0x0F00,DID1),0x400))
+ {
+ Store(0x1, EDPV)
+ Store(DID1, DIDX)
+ Return(1)
+ }
+ If(LEqual(DID1,0))
+ {
+ Return(1)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DID1))
+ }
+ }
+
+ // Return the Current Status.
+
+ Method(_DCS,0)
+ {
+ Return(CDDS(DID1))
+ }
+
+ // Query Graphics State (active or inactive).
+
+ Method(_DGS,0)
+ {
+ Return(NDDS(DID1))
+ }
+
+ // Device Set State.
+
+ // _DSS Table:
+ //
+ // BIT31 BIT30 Execution
+ // 0 0 Don't implement.
+ // 0 1 Cache change. Nothing to Implement.
+ // 1 0 Don't Implement.
+ // 1 1 Display Switch Complete. Implement.
+
+ Method(_DSS,1)
+ {
+ If(LEqual(And(Arg0,0xC0000000),0xC0000000))
+ {
+
+ // State change was performed by the
+ // Video Drivers. Simply update the
+ // New State.
+
+ Store(NSTE,CSTE)
+ }
+ }
+}
+
+Device(DD02)
+{
+
+ // Return Unique ID.
+
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(And(0x0F00,DID2),0x400))
+ {
+ Store(0x2, EDPV)
+ Store(DID2, DIDX)
+ Return(2)
+ }
+ If(LEqual(DID2,0))
+ {
+ Return(2)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DID2))
+ }
+ }
+
+ // Return the Current Status.
+
+ Method(_DCS,0)
+ {
+ Return(CDDS(DID2))
+ }
+
+ // Query Graphics State (active or inactive).
+
+ Method(_DGS,0)
+ {
+ // Return the Next State.
+ Return(NDDS(DID2))
+ }
+
+ // Device Set State. (See table above.)
+
+ Method(_DSS,1)
+ {
+ If(LEqual(And(Arg0,0xC0000000),0xC0000000))
+ {
+
+ // State change was performed by the
+ // Video Drivers. Simply update the
+ // New State.
+
+ Store(NSTE,CSTE)
+ }
+ }
+}
+
+Device(DD03)
+{
+
+ // Return Unique ID.
+
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(And(0x0F00,DID3),0x400))
+ {
+ Store(0x3, EDPV)
+ Store(DID3, DIDX)
+ Return(3)
+ }
+ If(LEqual(DID3,0))
+ {
+ Return(3)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DID3))
+ }
+ }
+
+ // Return the Current Status.
+
+ Method(_DCS,0)
+ {
+ If(LEqual(DID3,0))
+ {
+ Return(0x0B)
+ }
+ Else
+ {
+ Return(CDDS(DID3))
+ }
+ }
+
+ // Query Graphics State (active or inactive).
+
+ Method(_DGS,0)
+ {
+ Return(NDDS(DID3))
+ }
+
+ // Device Set State. (See table above.)
+
+ Method(_DSS,1)
+ {
+ If(LEqual(And(Arg0,0xC0000000),0xC0000000))
+ {
+ // State change was performed by the
+ // Video Drivers. Simply update the
+ // New State.
+
+ Store(NSTE,CSTE)
+ }
+ }
+}
+
+Device(DD04)
+{
+
+ // Return Unique ID.
+
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(And(0x0F00,DID4),0x400))
+ {
+ Store(0x4, EDPV)
+ Store(DID4, DIDX)
+ Return(4)
+ }
+ If(LEqual(DID4,0))
+ {
+ Return(4)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DID4))
+ }
+ }
+
+ // Return the Current Status.
+
+ Method(_DCS,0)
+ {
+ If(LEqual(DID4,0))
+ {
+ Return(0x0B)
+ }
+ Else
+ {
+ Return(CDDS(DID4))
+ }
+ }
+
+ // Query Graphics State (active or inactive).
+
+ Method(_DGS,0)
+ {
+ Return(NDDS(DID4))
+ }
+
+ // Device Set State. (See table above.)
+
+ Method(_DSS,1)
+ {
+ If(LEqual(And(Arg0,0xC0000000),0xC0000000))
+ {
+
+ // State change was performed by the
+ // Video Drivers. Simply update the
+ // New State.
+
+ Store(NSTE,CSTE)
+ }
+ }
+}
+
+
+Device(DD05)
+{
+
+ // Return Unique ID.
+
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(And(0x0F00,DID5),0x400))
+ {
+ Store(0x5, EDPV)
+ Store(DID5, DIDX)
+ Return(5)
+ }
+ If(LEqual(DID5,0))
+ {
+ Return(5)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DID5))
+ }
+ }
+
+ // Return the Current Status.
+
+ Method(_DCS,0)
+ {
+ If(LEqual(DID5,0))
+ {
+ Return(0x0B)
+ }
+ Else
+ {
+ Return(CDDS(DID5))
+ }
+ }
+
+ // Query Graphics State (active or inactive).
+
+ Method(_DGS,0)
+ {
+ Return(NDDS(DID5))
+ }
+
+ // Device Set State. (See table above.)
+
+ Method(_DSS,1)
+ {
+ If(LEqual(And(Arg0,0xC0000000),0xC0000000))
+ {
+ // State change was performed by the
+ // Video Drivers. Simply update the
+ // New State.
+
+ Store(NSTE,CSTE)
+ }
+ }
+}
+
+
+Device(DD06)
+{
+
+ // Return Unique ID.
+
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(And(0x0F00,DID6),0x400))
+ {
+ Store(0x6, EDPV)
+ Store(DID6, DIDX)
+ Return(6)
+ }
+ If(LEqual(DID6,0))
+ {
+ Return(6)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DID6))
+ }
+ }
+
+ // Return the Current Status.
+
+ Method(_DCS,0)
+ {
+ If(LEqual(DID6,0))
+ {
+ Return(0x0B)
+ }
+ Else
+ {
+ Return(CDDS(DID6))
+ }
+ }
+
+ // Query Graphics State (active or inactive).
+
+ Method(_DGS,0)
+ {
+ Return(NDDS(DID6))
+ }
+
+ // Device Set State. (See table above.)
+
+ Method(_DSS,1)
+ {
+ If(LEqual(And(Arg0,0xC0000000),0xC0000000))
+ {
+ // State change was performed by the
+ // Video Drivers. Simply update the
+ // New State.
+
+ Store(NSTE,CSTE)
+ }
+ }
+}
+
+
+Device(DD07)
+{
+
+ // Return Unique ID.
+
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(And(0x0F00,DID7),0x400))
+ {
+ Store(0x7, EDPV)
+ Store(DID7, DIDX)
+ Return(7)
+ }
+ If(LEqual(DID7,0))
+ {
+ Return(7)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DID7))
+ }
+ }
+
+ // Return the Current Status.
+
+ Method(_DCS,0)
+ {
+ If(LEqual(DID7,0))
+ {
+ Return(0x0B)
+ }
+ Else
+ {
+ Return(CDDS(DID7))
+ }
+ }
+
+ // Query Graphics State (active or inactive).
+
+ Method(_DGS,0)
+ {
+ Return(NDDS(DID7))
+ }
+
+ // Device Set State. (See table above.)
+
+ Method(_DSS,1)
+ {
+ If(LEqual(And(Arg0,0xC0000000),0xC0000000))
+ {
+ // State change was performed by the
+ // Video Drivers. Simply update the
+ // New State.
+
+ Store(NSTE,CSTE)
+ }
+ }
+}
+
+
+Device(DD08)
+{
+
+ // Return Unique ID.
+
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(And(0x0F00,DID8),0x400))
+ {
+ Store(0x8, EDPV)
+ Store(DID8, DIDX)
+ Return(8)
+ }
+ If(LEqual(DID8,0))
+ {
+ Return(8)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DID8))
+ }
+ }
+
+ // Return the Current Status.
+
+ Method(_DCS,0)
+ {
+ If(LEqual(DID8,0))
+ {
+ Return(0x0B)
+ }
+ Else
+ {
+ Return(CDDS(DID8))
+ }
+ }
+
+ // Query Graphics State (active or inactive).
+
+ Method(_DGS,0)
+ {
+ Return(NDDS(DID8))
+ }
+
+ // Device Set State. (See table above.)
+
+ Method(_DSS,1)
+ {
+ If(LEqual(And(Arg0,0xC0000000),0xC0000000))
+ {
+ // State change was performed by the
+ // Video Drivers. Simply update the
+ // New State.
+
+ Store(NSTE,CSTE)
+ }
+ }
+}
+
+//device for eDP
+Device(DD1F)
+{
+ // Return Unique ID.
+
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(EDPV, 0x0))
+ {
+ Return(0x1F)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DIDX))
+ }
+ }
+
+ // Return the Current Status.
+
+ Method(_DCS,0)
+ {
+ If(LEqual(EDPV, 0x0))
+ {
+ Return(0x00)
+ }
+ Else
+ {
+ Return(CDDS(DIDX))
+ }
+ }
+
+ // Query Graphics State (active or inactive).
+
+ Method(_DGS,0)
+ {
+ Return(NDDS(DIDX))
+ }
+
+ // Device Set State. (See table above.)
+
+ Method(_DSS,1)
+ {
+ If(LEqual(And(Arg0,0xC0000000),0xC0000000))
+ {
+ // State change was performed by the
+ // Video Drivers. Simply update the
+ // New State.
+ Store(NSTE,CSTE)
+ }
+ }
+ // Query List of Brightness Control Levels Supported.
+
+ Method(_BCL,0)
+ {
+ // List of supported brightness levels in the following sequence.
+
+ // Level when machine has full power.
+ // Level when machine is on batteries.
+ // Other supported levels.
+ Return(Package() {80, 50, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53,
54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73,
74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93,
94, 95, 96, 97, 98, 99, 100})
+ }
+
+ // Set the Brightness Level.
+
+ Method (_BCM,1)
+ {
+ // Set the requested level if it is between 0 and 100%.
+
+ If(LAnd(LGreaterEqual(Arg0,0),LLessEqual(Arg0,100)))
+ {
+ \_SB.PCI0.GFX0.AINT(1, Arg0)
+ Store(Arg0,BRTL) // Store Brightness Level.
+ }
+ }
+
+ // Brightness Query Current level.
+
+ Method (_BQC,0)
+ {
+ Return(BRTL)
+ }
+}
+
+Method(SDDL,1)
+{
+ Increment(NDID)
+ Store(And(Arg0,0xF0F),Local0)
+ Or(0x80000000,Local0, Local1)
+ If(LEqual(DIDL,Local0))
+ {
+ Return(Local1)
+ }
+ If(LEqual(DDL2,Local0))
+ {
+ Return(Local1)
+ }
+ If(LEqual(DDL3,Local0))
+ {
+ Return(Local1)
+ }
+ If(LEqual(DDL4,Local0))
+ {
+ Return(Local1)
+ }
+ If(LEqual(DDL5,Local0))
+ {
+ Return(Local1)
+ }
+ If(LEqual(DDL6,Local0))
+ {
+ Return(Local1)
+ }
+ If(LEqual(DDL7,Local0))
+ {
+ Return(Local1)
+ }
+ If(LEqual(DDL8,Local0))
+ {
+ Return(Local1)
+ }
+ Return(0)
+}
+
+Method(CDDS,1)
+{
+ Store(And(Arg0,0xF0F),Local0)
+
+ If(LEqual(0, Local0))
+ {
+ Return(0x1D)
+ }
+ If(LEqual(CADL, Local0))
+ {
+ Return(0x1F)
+ }
+ If(LEqual(CAL2, Local0))
+ {
+ Return(0x1F)
+ }
+ If(LEqual(CAL3, Local0))
+ {
+ Return(0x1F)
+ }
+ If(LEqual(CAL4, Local0))
+ {
+ Return(0x1F)
+ }
+ If(LEqual(CAL5, Local0))
+ {
+ Return(0x1F)
+ }
+ If(LEqual(CAL6, Local0))
+ {
+ Return(0x1F)
+ }
+ If(LEqual(CAL7, Local0))
+ {
+ Return(0x1F)
+ }
+ If(LEqual(CAL8, Local0))
+ {
+ Return(0x1F)
+ }
+ Return(0x1D)
+}
+
+Method(NDDS,1)
+{
+ Store(And(Arg0,0xF0F),Local0)
+
+ If(LEqual(0, Local0))
+ {
+ Return(0)
+ }
+ If(LEqual(NADL, Local0))
+ {
+ Return(1)
+ }
+ If(LEqual(NDL2, Local0))
+ {
+ Return(1)
+ }
+ If(LEqual(NDL3, Local0))
+ {
+ Return(1)
+ }
+ If(LEqual(NDL4, Local0))
+ {
+ Return(1)
+ }
+ If(LEqual(NDL5, Local0))
+ {
+ Return(1)
+ }
+ If(LEqual(NDL6, Local0))
+ {
+ Return(1)
+ }
+ If(LEqual(NDL7, Local0))
+ {
+ Return(1)
+ }
+ If(LEqual(NDL8, Local0))
+ {
+ Return(1)
+ }
+ Return(0)
+}
+
+//
+// Include IGD OpRegion/Software SCI interrupt handler which is use by
+// the graphics drivers to request data from system BIOS.
+//
+include("IgdOpRn.ASL")
Added: trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/INTELISPDev2.ASL
===================================================================
--- trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/INTELISPDev2.ASL
(rev 0)
+++ trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/INTELISPDev2.ASL
2015-01-12 09:37:20 UTC (rev 16599)
@@ -0,0 +1,77 @@
+/*++
+
+Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
+
+ This program and the accompanying materials are licensed and made available
under
+ the terms and conditions of the BSD License that accompanies this
distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+Module Name:
+
+ INTELISPDev2.ASL
+
+Abstract:
+
+ ISP Exist as B0D2F0 Software ACPI Reference Code for the Baytrail Family.
+
+--*/
+////Device ISP0
+Device(ISP0)
+{
+ Name(_ADR, 0x0F38)
+ //Name (_HID, "80860F38")
+ //Name (_CID, "80860F38")
+ Name(_DDN, "VLV2 ISP - 80860F38")
+ Name(_UID, 0x01)
+
+ Method (_STA, 0, NotSerialized)
+ {
+ If(LEqual(ISPD,1)) //Dev2 need report ISP0 as GFX0 child
+ {
+ Return (0xF)
+ }
+ Else
+ {
+ Return (0x0)
+ }
+ }
+ Name(SBUF,ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0x00000000, 0x00400000, ISP0)
+ })
+ Method(_CRS, 0x0, NotSerialized)
+ {
+ Return (SBUF)
+ }
+ Method (_SRS, 0x1, NotSerialized)
+ {
+ }
+ Method (_DIS, 0x0, NotSerialized)
+ {
+ }
+ Method(_DSM, 0x4, NotSerialized)
+ {
+ If (LEqual (Arg0, 0x01))
+ {
+ ///Switch ISP to D3H
+ Return (0x01)
+ }
+ Elseif (LEqual (Arg0, 0x02))
+ {
+ //Switch ISP to D0
+ Return (0x02)
+ }
+ Else
+ {
+ //Do nothing
+ Return (0x0F)
+ }
+ }
+} ///End ISP0
+
Added: trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOGBDA.ASL
===================================================================
--- trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOGBDA.ASL
(rev 0)
+++ trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOGBDA.ASL 2015-01-12
09:37:20 UTC (rev 16599)
@@ -0,0 +1,161 @@
+/*++
+
+Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
+
+ This program and the accompanying materials are licensed and made available
under
+ the terms and conditions of the BSD License that accompanies this
distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+Module Name:
+
+ IgdOGBDA.ASL
+
+Abstract:
+
+ IGD OpRegion/Software SCI Reference Code for the Baytrail Family.
+ This file contains Get BIOS Data Area funciton support for
+ the Integrated Graphics Device (IGD) OpRegion/Software SCI mechanism.
+
+--*/
+
+
+Method (GBDA, 0, Serialized)
+{
+
+ // Supported calls: Sub-function 0
+
+ If (LEqual(GESF, 0))
+ {
+ //<TODO> Update implementation specific supported calls. Reference
+ // code is set to Intel's validated implementation.
+
+ Store(0x0000279, PARM)
+
+ Store(Zero, GESF) // Clear the exit parameter
+ Return(SUCC) // Success
+ }
+
+ // Requested callbacks: Sub-function 1
+
+ If (LEqual(GESF, 1))
+ {
+
+ //<TODO> Update implementation specific system BIOS requested call
+ // back functions. Call back functions are where the driver calls the
+ // system BIOS at function indicated event.
+
+ Store(0x00000240, PARM)
+
+ Store(Zero, GESF) // Clear the exit parameter
+ Return(SUCC) // Success
+ }
+
+ // Get Boot display Preferences: Sub-function 4
+
+ If (LEqual(GESF, 4))
+ {
+
+ //<TODO> Update the implementation specific Get Boot Display
+ // Preferences function.
+
+ And(PARM, 0xEFFF0000, PARM) // PARM[30:16] = Boot device ports
+ And(PARM, ShiftLeft(DeRefOf(Index(DBTB, IBTT)), 16), PARM)
+ Or(IBTT, PARM, PARM) // PARM[7:0] = Boot device type
+
+ Store(Zero, GESF) // Clear the exit parameter
+ Return(SUCC) // Success
+ }
+
+ // Panel details: Sub-function 5
+
+ If (LEqual(GESF, 5))
+ {
+
+ //<TODO> Update the implementation specific Get Panel Details
+ // function.
+
+ Store(IPSC, PARM) // Report the scaling setting
+ Or(PARM, ShiftLeft(IPAT, 8), PARM)
+ Add(PARM, 0x100, PARM) // Adjust panel type, 0 = VBT default
+ Or(PARM, ShiftLeft(LIDS, 16), PARM) // Report the lid state
+ Add(PARM, 0x10000, PARM) // Adjust the lid state, 0 = Unknown
+ Or(PARM, ShiftLeft(IBLC, 18), PARM) // Report the BLC setting
+ Or(PARM, ShiftLeft(IBIA, 20), PARM) // Report the BIA setting
+ Store(Zero, GESF)
+ Return(SUCC)
+ }
+
+ // TV-standard/Video-connector: Sub-function 6
+
+ If (LEqual(GESF, 6))
+ {
+
+ //<TODO> Update the implementation specific Get
+ // TV-standard/Video-connectorPanel function.
+
+ Store(ITVF, PARM)
+ Or(PARM, ShiftLeft(ITVM, 4), PARM)
+ Store(Zero, GESF)
+ Return(SUCC)
+ }
+
+ // Internal graphics: Sub-function 7
+
+ If (LEqual(GESF, 7))
+ {
+ Store(GIVD, PARM) // PARM[0] - VGA mode(1=VGA)
+ Xor(PARM, 1, PARM) // Invert the VGA mode polarity
+ Or(PARM, ShiftLeft(GMFN, 1), PARM) // PARM[1] - # IGD PCI functions-1
+ // PARM[3:2] - Reserved
+ // PARM[4] - IGD D3 support(0=cold)
+ // PARM[10:5] - Reserved
+ Or(PARM, ShiftLeft(3, 11), PARM) // PARM[12:11] - DVMT mode(11b = 5.0)
+
+ //
+ // Report DVMT 5.0 Total Graphics memory size.
+ //
+ Or(PARM, ShiftLeft(IDMS, 17), PARM) // Bits 20:17 are for Gfx total
memory size
+
+ // If the "Set Internal Graphics" call is supported, the modified
+ // settings flag must be programmed per the specification. This means
+ // that the flag must be set to indicate that system BIOS requests
+ // these settings. Once "Set Internal Graphics" is called, the
+ // modified settings flag must be cleared on all subsequent calls to
+ // this function.
+
+ // Report the graphics frequency based on DISPLAY_CLOCK_FREQUENCY_ENCODING
[MMADR+0x20C8]
+
+ Or(ShiftLeft(Derefof(Index(CDCT, \_SB.PCI0.GFX0.MCHK.DCFE)), 21),PARM,
PARM)
+
+ Store(1, GESF) // Set the modified settings flag
+ Return(SUCC)
+ }
+
+ // Spread spectrum clocks: Sub-function 10
+
+ If (LEqual(GESF, 10))
+ {
+
+ Store(0, PARM) // Assume SSC is disabled
+
+ If(ISSC)
+ {
+ Or(PARM, 3, PARM) // If SSC enabled, return SSC1+Enabled
+ }
+
+ Store(0, GESF) // Set the modified settings flag
+ Return(SUCC) // Success
+ }
+
+
+ // A call to a reserved "Get BIOS data" function was received.
+
+ Store(Zero, GESF) // Clear the exit parameter
+ Return(CRIT) // Reserved, "Critical failure"
+}
Added: trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOMOBF.ASL
===================================================================
--- trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOMOBF.ASL
(rev 0)
+++ trunk/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOMOBF.ASL 2015-01-12
09:37:20 UTC (rev 16599)
@@ -0,0 +1,491 @@
+/*++
+
+Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
+
+ This program and the accompanying materials are licensed and made available
under
+ the terms and conditions of the BSD License that accompanies this
distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+Module Name:
+
+ IgdOMOBF.ASL
+
+Abstract:
+
+ IGD OpRegion/Software SCI Reference Code for the Baytrail Family.
+ This file contains ASL code with the purpose of handling events
+ i.e. hotkeys and other system interrupts.
+
+--*/
+
+
+// Notes:
+// 1. The following routines are to be called from the appropriate event
+// handlers.
+// 2. This code cannot comprehend the exact implementation in the OEM's BIOS.
+// Therefore, an OEM must call these methods from the existing event
+// handler infrastructure. Details on when/why to call each method is
+// included in the method header under the "usage" section.
+
+
+/************************************************************************;
+;* ACPI Notification Methods
+;************************************************************************/
+
+
+/************************************************************************;
+;*
+;* Name: PDRD
+;*
+;* Description: Check if the graphics driver is ready to process
+;* notifications and video extensions.
+;*
+;* Usage: This method is to be called prior to performing any
+;* notifications or handling video extensions.
+;* Ex: If (PDRD()) {Return (FAIL)}
+;*
+;* Input: None
+;*
+;* Output: None
+;*
+;* References: DRDY (Driver ready status), ASLP (Driver recommended
+;* sleep timeout value).
+;*
+;************************************************************************/
+
+Method(PDRD)
+{
+ If(LNot(DRDY))
+ {
+
+ // Sleep for ASLP milliseconds if the driver is not ready.
+
+ Sleep(ASLP)
+ }
+
+ // If DRDY is clear, the driver is not ready. If the return value is
+ // !=0, do not perform any notifications or video extension handling.
+
+ Return(LNot(DRDY))
+}
+
+
+/************************************************************************;
+;*
+;* Name: PSTS
+;*
+;* Description: Check if the graphics driver has completed the previous
+;* "notify" command.
+;*
+;* Usage: This method is called before every "notify" command. A
+;* "notify" should only be set if the driver has completed the
+;* previous command. Else, ignore the event and exit the parent
+;* method.
+;* Ex: If (PSTS()) {Return (FAIL)}
+;*
+;* Input: None
+;*
+;* Output: None
+;*
+;* References: CSTS (Notification status), ASLP (Driver recommended sleep
+;* timeout value).
+;*
+;************************************************************************/
+
+Method(PSTS)
+{
+ If(LGreater(CSTS, 2))
+ {
+ // Sleep for ASLP milliseconds if the status is not "success,
+ // failure, or pending"
+ //
+ Sleep(ASLP)
+ }
+
+ Return(LEqual(CSTS, 3)) // Return True if still Dispatched
+}
+
+
+/************************************************************************;
+;*
+;* Name: GNOT
+;*
+;* Description: Call the appropriate methods to query the graphics driver
+;* status. If all methods return success, do a notification of
+;* the graphics device.
+;*
+;* Usage: This method is to be called when a graphics device
+;* notification is required (display switch hotkey, etc).
+;*
+;* Input: Arg0 = Current event type:
+;* 1 = display switch
+;* 2 = lid
+;* 3 = dock
+;* Arg1 = Notification type:
+;* 0 = Re-enumeration
+;* 0x80 = Display switch
+;*
+;* Output: Returns 0 = success, 1 = failure
+;*
+;* References: PDRD and PSTS methods. OSYS (OS version)
+;*
+;************************************************************************/
+
+Method(GNOT, 2)
+{
+ // Check for 1. Driver loaded, 2. Driver ready.
+ // If any of these cases is not met, skip this event and return failure.
+ //
+ If(PDRD())
+ {
+ Return(0x1) // Return failure if driver not loaded.
+ }
+
+ Store(Arg0, CEVT) // Set up the current event value
+ Store(3, CSTS) // CSTS=BIOS dispatched an event
+
+ If(LAnd(LEqual(CHPD, 0), LEqual(Arg1, 0))) // Do not re-enum if driver
supports hotplug
+ {
+ If(LOr(LGreater(OSYS, 2000), LLess(OSYS, 2006)))
+ {
+ //
+ // WINXP requires that the entire PCI Bridge be re-enumerated.
+ //
+ Notify(\_SB.PCI0, Arg1)
+ }
+ Else
+ {
+ //
+ // Re-enumerate the Graphics Device for non-XP operating systems.
+ //
+ Notify(\_SB.PCI0.GFX0, Arg1)
+ }
+ }
+
+ Notify(\_SB.PCI0.GFX0,0x80)
+
+
+ Return(0x0) // Return success
+}
+
+
+/************************************************************************;
+;*
+;* Name: GHDS
+;*
+;* Description: Handle a hotkey display switching event (performs a
+;* Notify(GFX0, 0).
+;*
+;* Usage: This method must be called when a hotkey event occurs and the
+;* purpose of that hotkey is to do a display switch.
+;*
+;* Input: Arg0 = Toggle table number.
+;*
+;* Output: Returns 0 = success, 1 = failure.
+;* CEVT and TIDX are indirect outputs.
+;*
+;* References: TIDX, GNOT
+;*
+;************************************************************************/
+
+Method(GHDS, 1)
+{
+ Store(Arg0, TIDX) // Store the table number
+
+ // Call GNOT for CEVT = 1 = hotkey, notify value = 0
+
+ Return(GNOT(1, 0)) // Return stats from GNOT
+}
+
+
+/************************************************************************;
+;*
+;* Name: GLID
+;*
+;* Description: Handle a lid event (performs the Notify(GFX0, 0), but not the
+;* lid notify).
+;*
+;* Usage: This method must be called when a lid event occurs. A
+;* Notify(LID0, 0x80) must follow the call to this method.
+;*
+;* Input: Arg0 = Lid state:
+;* 0 = All closed
+;* 1 = internal LFP lid open
+;* 2 = external lid open
+;* 3 = both external and internal open
+;*
+;* Output: Returns 0=success, 1=failure.
+;* CLID and CEVT are indirect outputs.
+;*
+;* References: CLID, GNOT
+;*
+;************************************************************************/
+
+Method(GLID, 1)
+{
+ Store(Arg0, CLID) // Store the current lid state
+
+ // Call GNOT for CEVT=2=Lid, notify value = 0
+
+ Return(GNOT(2, 0)) // Return stats from GNOT
+}
+
+
+/************************************************************************;
+;*
+;* Name: GDCK
+;*
+;* Description: Handle a docking event by updating the current docking status
+;* and doing a notification.
+;*
+;* Usage: This method must be called when a docking event occurs.
+;*
+;* Input: Arg0 = Docking state:
+;* 0 = Undocked
+;* 1 = Docked
+;*
+;* Output: Returns 0=success, 1=failure.
+;* CDCK and CEVT are indirect outputs.
+;*
+;* References: CDCK, GNOT
+;*
+;************************************************************************/
+
+Method(GDCK, 1)
+{
+ Store(Arg0, CDCK) // Store the current dock state
+
+ // Call GNOT for CEVT=4=Dock, notify value = 0
+
+ Return(GNOT(4, 0)) // Return stats from GNOT
+}
+
+
+/************************************************************************;
+;* ASLE Interrupt Methods
+;************************************************************************/
+
+
+/************************************************************************;
+;*
+;* Name: PARD
+;*
+;* Description: Check if the driver is ready to handle ASLE interrupts
+;* generate by the system BIOS.
+;*
+;* Usage: This method must be called before generating each ASLE
+;* interrupt.
+;*
+;* Input: None
+;*
+;* Output: Returns 0 = success, 1 = failure.
+;*
+;* References: ARDY (Driver readiness), ASLP (Driver recommended sleep
+;* timeout value)
+;*
+;************************************************************************/
+
+Method(PARD)
+{
+ If(LNot(ARDY))
+ {
+
+ // Sleep for ASLP milliseconds if the driver is not ready.
+
+ Sleep(ASLP)
+ }
+
+ // If ARDY is clear, the driver is not ready. If the return value is
+ // !=0, do not generate the ASLE interrupt.
+
+ Return(LNot(ARDY))
+}
+
+
+/************************************************************************;
+;*
+;* Name: AINT
+;*
+;* Description: Call the appropriate methods to generate an ASLE interrupt.
+;* This process includes ensuring the graphics driver is ready
+;* to process the interrupt, ensuring the driver supports the
+;* interrupt of interest, and passing information about the event
+;* to the graphics driver.
+;*
+;* Usage: This method must called to generate an ASLE interrupt.
+;*
+;* Input: Arg0 = ASLE command function code:
+;* 0 = Set ALS illuminance
+;* 1 = Set backlight brightness
+;* 2 = Do Panel Fitting
+;* Arg1 = If Arg0 = 0, current ALS reading:
+;* 0 = Reading below sensor range
+;* 1-0xFFFE = Current sensor reading
+;* 0xFFFF = Reading above sensor range
+;* Arg1 = If Arg0 = 1, requested backlight percentage
+;*
+;* Output: Returns 0 = success, 1 = failure
+;*
+;* References: PARD method.
+;*
+;************************************************************************/
+
+Method(AINT, 2)
+{
+
+ // Return failure if the requested feature is not supported by the
+ // driver.
+
+ If(LNot(And(TCHE, ShiftLeft(1, Arg0))))
+ {
+ Return(0x1)
+ }
+
+ // Return failure if the driver is not ready to handle an ASLE
+ // interrupt.
+
+ If(PARD())
+ {
+ Return(0x1)
+ }
+
+ // Evaluate the first argument (Panel fitting, backlight brightness, or ALS).
+
+ If(LEqual(Arg0, 2)) // Arg0 = 2, so request a panel fitting mode
change.
+ {
+ If(CPFM) // If current mode field
is non-zero use it.
+ {
+ And(CPFM, 0x0F, Local0) // Create variables without
reserved
+ And(EPFM, 0x0F, Local1) // or valid bits.
+
+ If(LEqual(Local0, 1)) // If current mode is centered,
+ {
+ If(And(Local1, 6)) // and if stretched is enabled,
+ {
+ Store(6, PFIT) // request stretched.
+ }
+ Else // Otherwise,
+ {
+ If(And(Local1, 8)) // if aspect ratio is enabled,
+ {
+ Store(8, PFIT) // request aspect ratio.
+ }
+ Else // Only centered mode is enabled
+ {
+ Store(1, PFIT) // so request centered. (No change.)
+ }
+ }
+ }
+ If(LEqual(Local0, 6)) // If current mode is stretched,
+ {
+ If(And(Local1, 8)) // and if aspect ratio is enabled,
+ {
+ Store(8, PFIT) // request aspect ratio.
+ }
+ Else // Otherwise,
+ {
+ If(And(Local1, 1)) // if centered is enabled,
+ {
+ Store(1, PFIT) // request centered.
+ }
+ Else // Only stretched mode is enabled
+ {
+ Store(6, PFIT) // so request stretched. (No change.)
+ }
+ }
+ }
+ If(LEqual(Local0, 8)) // If current mode is aspect
ratio,
+ {
+ If(And(Local1, 1)) // and if centered is enabled,
+ {
+ Store(1, PFIT) // request centered.
+ }
+ Else // Otherwise,
+ {
+ If(And(Local1, 6)) // if stretched is enabled,
+ {
+ Store(6, PFIT) // request stretched.
+ }
+ Else // Only aspect ratio mode is enabled
+ {
+ Store(8, PFIT) // so request aspect ratio. (No change.)
+ }
+ }
+ }
+ }
+
+ // The following code for panel fitting (within the Else condition) is
retained for backward compatiblity.
+
+ Else // If CFPM field is zero use PFIT and
toggle the
+ {
+ Xor(PFIT,7,PFIT) // mode setting between stretched and centered
only.
+ }
+
+ Or(PFIT,0x80000000,PFIT) // Set the valid bit for all cases.
+
+ Store(4, ASLC) // Store "Panel fitting event" to
ASLC[31:1]
+ }
+ Else
+ {
+ If(LEqual(Arg0, 1)) // Arg0=1, so set the backlight brightness.
+ {
+ Store(Divide(Multiply(Arg1, 255), 100), BCLP) // Convert from percent to
0-255.
+
+ Or(BCLP, 0x80000000, BCLP) // Set the valid bit.
+
+ Store(2, ASLC) // Store "Backlight control event" to
ASLC[31:1]
+ }
+ Else
+ {
+ If(LEqual(Arg0, 0)) // Arg0=0, so set the ALS illuminace
+ {
+ Store(Arg1, ALSI)
+
+ Store(1, ASLC) // Store "ALS event" to ASLC[31:1]
+ }
+ Else
+ {
+ Return(0x1) // Unsupported function
+ }
+ }
+ }
+
+ Store(0x01, ASLE) // Generate ASLE interrupt
+ Return(0x0) // Return success
+}
+
+
+/************************************************************************;
+;*
+;* Name: SCIP
+;*
+;* Description: Checks the presence of the OpRegion and SCI
+;*
+;* Usage: This method is called before other OpRegion methods. The
+;* former "GSMI True/False is not always valid. This method
+;* checks if the OpRegion Version is non-zero and if non-zero,
+;* (present and readable) then checks the GSMI flag.
+;*
+;* Input: None
+;*
+;* Output: Boolean True = SCI present.
+;*
+;* References: None
+;*
@@ Diff output truncated at 100000 characters. @@
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