Revision: 16891
http://sourceforge.net/p/edk2/code/16891
Author: lersek
Date: 2015-02-23 16:02:34 +0000 (Mon, 23 Feb 2015)
Log Message:
-----------
PcAtChipsetPkg/PciHostBridgeDxe: fix typo in "aperture"
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <[email protected]>
Acked-by: Olivier Martin <[email protected]>
Reviewed-by: Jordan Justen <[email protected]>
Modified Paths:
--------------
trunk/edk2/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.c
trunk/edk2/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.h
trunk/edk2/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c
Modified: trunk/edk2/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.c
===================================================================
--- trunk/edk2/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.c 2015-02-23
16:02:29 UTC (rev 16890)
+++ trunk/edk2/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.c 2015-02-23
16:02:34 UTC (rev 16891)
@@ -18,7 +18,7 @@
// Hard code: Root Bridge Number within the host bridge
// Root Bridge's attribute
// Root Bridge's device path
-// Root Bridge's resource appeture
+// Root Bridge's resource aperture
//
UINTN RootBridgeNumber[1] = { 1 };
@@ -52,7 +52,7 @@
}
};
-PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[1][1] = {
+PCI_ROOT_BRIDGE_RESOURCE_APERTURE mResAperture[1][1] = {
{{0, 0xff, 0x80000000, 0xffffffff, 0, 0xffff}}
};
@@ -145,7 +145,7 @@
&PrivateData->Io,
HostBridge->HostBridgeHandle,
RootBridgeAttribute[Loop1][Loop2],
- &mResAppeture[Loop1][Loop2]
+ &mResAperture[Loop1][Loop2]
);
Status = gBS->InstallMultipleProtocolInterfaces(
Modified: trunk/edk2/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.h
===================================================================
--- trunk/edk2/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.h 2015-02-23
16:02:29 UTC (rev 16890)
+++ trunk/edk2/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.h 2015-02-23
16:02:34 UTC (rev 16891)
@@ -403,7 +403,7 @@
UINT64 IoBase;
UINT64 IoLimit;
-} PCI_ROOT_BRIDGE_RESOURCE_APPETURE;
+} PCI_ROOT_BRIDGE_RESOURCE_APERTURE;
typedef enum {
TypeIo = 0,
@@ -482,7 +482,7 @@
@param Protocol Point to protocol instance
@param HostBridgeHandle Handle of host bridge
@param Attri Attribute of host bridge
- @param ResAppeture ResourceAppeture for host bridge
+ @param ResAperture ResourceAperture for host bridge
@retval EFI_SUCCESS Success to initialize the Pci Root Bridge.
@@ -492,7 +492,7 @@
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol,
IN EFI_HANDLE HostBridgeHandle,
IN UINT64 Attri,
- IN PCI_ROOT_BRIDGE_RESOURCE_APPETURE *ResAppeture
+ IN PCI_ROOT_BRIDGE_RESOURCE_APERTURE *ResAperture
);
#endif
Modified: trunk/edk2/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c
===================================================================
--- trunk/edk2/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c
2015-02-23 16:02:29 UTC (rev 16890)
+++ trunk/edk2/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c
2015-02-23 16:02:34 UTC (rev 16891)
@@ -621,7 +621,7 @@
@param Protocol Point to protocol instance
@param HostBridgeHandle Handle of host bridge
@param Attri Attribute of host bridge
- @param ResAppeture ResourceAppeture for host bridge
+ @param ResAperture ResourceAperture for host bridge
@retval EFI_SUCCESS Success to initialize the Pci Root Bridge.
@@ -631,7 +631,7 @@
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol,
IN EFI_HANDLE HostBridgeHandle,
IN UINT64 Attri,
- IN PCI_ROOT_BRIDGE_RESOURCE_APPETURE *ResAppeture
+ IN PCI_ROOT_BRIDGE_RESOURCE_APERTURE *ResAperture
)
{
EFI_STATUS Status;
@@ -644,21 +644,21 @@
// The host to pci bridge, the host memory and io addresses are
// direct mapped to pci addresses, so no need translate, set bases to 0.
//
- PrivateData->MemBase = ResAppeture->MemBase;
- PrivateData->IoBase = ResAppeture->IoBase;
+ PrivateData->MemBase = ResAperture->MemBase;
+ PrivateData->IoBase = ResAperture->IoBase;
//
// The host bridge only supports 32bit addressing for memory
// and standard IA32 16bit io
//
- PrivateData->MemLimit = ResAppeture->MemLimit;
- PrivateData->IoLimit = ResAppeture->IoLimit;
+ PrivateData->MemLimit = ResAperture->MemLimit;
+ PrivateData->IoLimit = ResAperture->IoLimit;
//
- // Bus Appeture for this Root Bridge (Possible Range)
+ // Bus Aperture for this Root Bridge (Possible Range)
//
- PrivateData->BusBase = ResAppeture->BusBase;
- PrivateData->BusLimit = ResAppeture->BusLimit;
+ PrivateData->BusBase = ResAperture->BusBase;
+ PrivateData->BusLimit = ResAperture->BusLimit;
//
// Specific for this chipset
------------------------------------------------------------------------------
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