Revision: 17596
http://sourceforge.net/p/edk2/code/17596
Author: abiesheuvel
Date: 2015-06-09 09:28:06 +0000 (Tue, 09 Jun 2015)
Log Message:
-----------
ArmPkg: reduce sysreg access count in GIC revision probe
Accesses to system registers are disproportionately heavy-weight
when executed under virtualization, since each one involves two
world switches (from guest to host and back again).
So change the sequence that enables the GIC SRE interface so that
it performs only a single sysreg read to test whether the SRE
interface is enabled already, and only performs a write and an
additional read if that turns out not to be the case.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <[email protected]>
Reviewed-by: Olivier Martin <[email protected]>
Modified Paths:
--------------
trunk/edk2/ArmPkg/Drivers/ArmGic/AArch64/ArmGicArchLib.c
trunk/edk2/ArmPkg/Drivers/ArmGic/Arm/ArmGicArchLib.c
Modified: trunk/edk2/ArmPkg/Drivers/ArmGic/AArch64/ArmGicArchLib.c
===================================================================
--- trunk/edk2/ArmPkg/Drivers/ArmGic/AArch64/ArmGicArchLib.c 2015-06-09
08:39:10 UTC (rev 17595)
+++ trunk/edk2/ArmPkg/Drivers/ArmGic/AArch64/ArmGicArchLib.c 2015-06-09
09:28:06 UTC (rev 17596)
@@ -23,6 +23,8 @@
VOID
)
{
+ UINT32 IccSre;
+
// Ideally we would like to use the GICC IIDR Architecture version here, but
// this does not seem to be very reliable as the implementation could easily
// get it wrong. It is more reliable to check if the GICv3 System Register
@@ -37,8 +39,12 @@
// Note: We do not need to set ICC_SRE_EL2.Enable because the OS is started
// at the same exception level.
// It is the OS responsibility to set this bit.
- ArmGicV3SetControlSystemRegisterEnable
(ArmGicV3GetControlSystemRegisterEnable () | ICC_SRE_EL2_SRE);
- if (ArmGicV3GetControlSystemRegisterEnable () & ICC_SRE_EL2_SRE) {
+ IccSre = ArmGicV3GetControlSystemRegisterEnable ();
+ if (!(IccSre & ICC_SRE_EL2_SRE)) {
+ ArmGicV3SetControlSystemRegisterEnable (IccSre | ICC_SRE_EL2_SRE);
+ IccSre = ArmGicV3GetControlSystemRegisterEnable ();
+ }
+ if (IccSre & ICC_SRE_EL2_SRE) {
return ARM_GIC_ARCH_REVISION_3;
}
}
Modified: trunk/edk2/ArmPkg/Drivers/ArmGic/Arm/ArmGicArchLib.c
===================================================================
--- trunk/edk2/ArmPkg/Drivers/ArmGic/Arm/ArmGicArchLib.c 2015-06-09
08:39:10 UTC (rev 17595)
+++ trunk/edk2/ArmPkg/Drivers/ArmGic/Arm/ArmGicArchLib.c 2015-06-09
09:28:06 UTC (rev 17596)
@@ -23,6 +23,8 @@
VOID
)
{
+ UINT32 IccSre;
+
// Ideally we would like to use the GICC IIDR Architecture version here, but
// this does not seem to be very reliable as the implementation could easily
// get it wrong. It is more reliable to check if the GICv3 System Register
@@ -37,8 +39,12 @@
// Note: We do not need to set ICC_SRE_EL2.Enable because the OS is started
// at the same exception level.
// It is the OS responsibility to set this bit.
- ArmGicV3SetControlSystemRegisterEnable
(ArmGicV3GetControlSystemRegisterEnable () | ICC_SRE_EL2_SRE);
- if (ArmGicV3GetControlSystemRegisterEnable () & ICC_SRE_EL2_SRE) {
+ IccSre = ArmGicV3GetControlSystemRegisterEnable ();
+ if (!(IccSre & ICC_SRE_EL2_SRE)) {
+ ArmGicV3SetControlSystemRegisterEnable (IccSre| ICC_SRE_EL2_SRE);
+ IccSre = ArmGicV3GetControlSystemRegisterEnable ();
+ }
+ if (IccSre & ICC_SRE_EL2_SRE) {
return ARM_GIC_ARCH_REVISION_3;
}
}
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