Revision: 17615
http://sourceforge.net/p/edk2/code/17615
Author: zwei4
Date: 2015-06-11 02:11:18 +0000 (Thu, 11 Jun 2015)
Log Message:
-----------
Add definitions for Protected Region 1 register.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Shifei Lu <[email protected]>
Reviewed-by: David Wei <[email protected]>
Modified Paths:
--------------
branches/UDK2014.SP1/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSpi.h
Modified:
branches/UDK2014.SP1/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSpi.h
===================================================================
---
branches/UDK2014.SP1/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSpi.h
2015-06-11 02:01:26 UTC (rev 17614)
+++
branches/UDK2014.SP1/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSpi.h
2015-06-11 02:11:18 UTC (rev 17615)
@@ -1,6 +1,6 @@
/**
-Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved
+Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved
This program and the accompanying materials are licensed and made available
under
the terms and conditions of the BSD License that accompanies this
distribution.
@@ -62,6 +62,12 @@
#define B_PCH_SPI_PR0_RPE BIT15 // Read Protection Enable
#define B_PCH_SPI_PR0_PRB_MASK 0x00001FFF // Protected Range
Base Mask, [12:0] here represents base limit of address [24:12]
+#define R_PCH_SPI_PR1 0x78 // Protected Region 1
Register
+#define B_PCH_SPI_PR1_WPE BIT31 // Write Protection Enable
+#define B_PCH_SPI_PR1_PRL_MASK 0x1FFF0000 // Protected Range
Limit Mask, [28:16] here represents upper limit of address [24:12]
+#define B_PCH_SPI_PR1_RPE BIT15 // Read Protection Enable
+#define B_PCH_SPI_PR1_PRB_MASK 0x00001FFF // Protected Range
Base Mask, [12:0] here represents base limit of address [24:12]
+
#define R_PCH_SPI_PREOP 0x94 // Prefix Opcode
Configuration Register (16 bits)
#define B_PCH_SPI_PREOP1_MASK 0xFF00 // Prefix Opcode 1 Mask
#define B_PCH_SPI_PREOP0_MASK 0x00FF // Prefix Opcode 0 Mask
------------------------------------------------------------------------------
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