Revision: 18585
http://sourceforge.net/p/edk2/code/18585
Author: abiesheuvel
Date: 2015-10-08 18:51:56 +0000 (Thu, 08 Oct 2015)
Log Message:
-----------
ArmPkg/AArch64Mmu: use architecturally correct definitions for XN/UXN
The non-privileged execute never (UXN) page table bit defined for the
EL1&0 translation regime and the execute never (XN) bit defined for the
EL2 and EL3 translation regimes happen to share the same bit position,
but they are in fact defined distinctly by the architecture. So define
both bits explicitly, and add comments in places where we take advantage
of the fact that they share the same bit position.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <[email protected]>
Reviewed-by: Leif Lindholm <[email protected]>
Modified Paths:
--------------
trunk/edk2/ArmPkg/Include/Chipset/AArch64Mmu.h
trunk/edk2/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
Modified: trunk/edk2/ArmPkg/Include/Chipset/AArch64Mmu.h
===================================================================
--- trunk/edk2/ArmPkg/Include/Chipset/AArch64Mmu.h 2015-10-08 09:29:56 UTC
(rev 18584)
+++ trunk/edk2/ArmPkg/Include/Chipset/AArch64Mmu.h 2015-10-08 18:51:56 UTC
(rev 18585)
@@ -75,12 +75,14 @@
#define TT_AF BIT10
#define TT_PXN_MASK BIT53
-#define TT_UXN_MASK BIT54
+#define TT_UXN_MASK BIT54 // EL1&0
+#define TT_XN_MASK BIT54 // EL2 / EL3
#define TT_ATTRIBUTES_MASK ((0xFFFULL << 52) | (0x3FFULL
<< 2))
#define TT_TABLE_PXN BIT59
-#define TT_TABLE_XN BIT60
+#define TT_TABLE_UXN BIT60 // EL1&0
+#define TT_TABLE_XN BIT60 // EL2 / EL3
#define TT_TABLE_NS BIT63
#define TT_TABLE_AP_MASK (BIT62 | BIT61)
Modified: trunk/edk2/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
===================================================================
--- trunk/edk2/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c 2015-10-08
09:29:56 UTC (rev 18584)
+++ trunk/edk2/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c 2015-10-08
18:51:56 UTC (rev 18585)
@@ -335,7 +335,8 @@
if (Attributes & TT_PXN_MASK) {
TableAttributes = TT_TABLE_PXN;
}
- if (Attributes & TT_UXN_MASK) {
+ // XN maps to UXN in the EL1&0 translation regime
+ if (Attributes & TT_XN_MASK) {
TableAttributes = TT_TABLE_XN;
}
if (Attributes & TT_NS) {
------------------------------------------------------------------------------
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