Revision: 18593
http://sourceforge.net/p/edk2/code/18593
Author: hwu1225
Date: 2015-10-09 07:03:24 +0000 (Fri, 09 Oct 2015)
Log Message:
-----------
MdePkg: Add ASSERT to handle local APIC not config properly
When the local APIC is not configurated properly, function
InternalX86GetInitTimerCount() may return zero, which will lead to a
divide by zero exception in SecPeiDxeTimerLibCpu.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <[email protected]>
Reviewed-by: Jeff Fan <[email protected]>
Modified Paths:
--------------
trunk/edk2/MdePkg/Library/SecPeiDxeTimerLibCpu/X86TimerLib.c
Modified: trunk/edk2/MdePkg/Library/SecPeiDxeTimerLibCpu/X86TimerLib.c
===================================================================
--- trunk/edk2/MdePkg/Library/SecPeiDxeTimerLibCpu/X86TimerLib.c
2015-10-09 06:03:34 UTC (rev 18592)
+++ trunk/edk2/MdePkg/Library/SecPeiDxeTimerLibCpu/X86TimerLib.c
2015-10-09 07:03:24 UTC (rev 18593)
@@ -1,7 +1,7 @@
/** @file
Timer Library functions built upon local APIC on IA32/x64.
- Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD
License
which accompanies this distribution. The full text of the license may be
found at
@@ -19,6 +19,7 @@
#include <Library/PcdLib.h>
#include <Library/DebugLib.h>
+#define APIC_SVR 0x0f0
#define APIC_LVTERR 0x370
#define APIC_TMICT 0x380
#define APIC_TMCCT 0x390
@@ -39,6 +40,11 @@
/**
Internal function to retrieve the base address of local APIC.
+ This function will ASSERT if:
+ The local APIC is not globally enabled.
+ The local APIC is not working under XAPIC mode.
+ The local APIC is not software enabled.
+
@return The base address of local APIC
**/
@@ -48,7 +54,32 @@
VOID
)
{
- return (UINTN)AsmMsrBitFieldRead64 (27, 12, 35) << 12;
+ UINTN MsrValue;
+ UINTN ApicBase;
+
+ MsrValue = (UINTN) AsmReadMsr64 (27);
+ ApicBase = MsrValue & 0xffffff000ULL;
+
+ //
+ // Check the APIC Global Enable bit (bit 11) in IA32_APIC_BASE MSR.
+ // This bit will be 1, if local APIC is globally enabled.
+ //
+ ASSERT ((MsrValue & BIT11) != 0);
+
+ //
+ // Check the APIC Extended Mode bit (bit 10) in IA32_APIC_BASE MSR.
+ // This bit will be 0, if local APIC is under XAPIC mode.
+ //
+ ASSERT ((MsrValue & BIT10) == 0);
+
+ //
+ // Check the APIC Software Enable/Disable bit (bit 8) in Spurious-Interrupt
+ // Vector Register.
+ // This bit will be 1, if local APIC is software enabled.
+ //
+ ASSERT ((MmioRead32 (ApicBase + APIC_SVR) & BIT8) != 0);
+
+ return ApicBase;
}
/**
@@ -109,6 +140,9 @@
Stalls the CPU for at least the given number of ticks. It's invoked by
MicroSecondDelay() and NanoSecondDelay().
+ This function will ASSERT if the APIC timer intial count returned from
+ InternalX86GetInitTimerCount() is zero.
+
@param ApicBase The base address of memory mapped registers of local APIC.
@param Delay A period of time to delay in ticks.
@@ -133,6 +167,7 @@
// Delay and the Init Count.
//
InitCount = InternalX86GetInitTimerCount (ApicBase);
+ ASSERT (InitCount != 0);
Times = Delay / (InitCount / 2);
Delay = Delay % (InitCount / 2);
------------------------------------------------------------------------------
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