Revision: 18752
http://sourceforge.net/p/edk2/code/18752
Author: abiesheuvel
Date: 2015-11-09 13:26:11 +0000 (Mon, 09 Nov 2015)
Log Message:
-----------
ArmPkg/ArmLib: remove unused ArmCleanDataCacheToPoU()
The function ArmCleanDataCacheToPoU() has no users, and its purpose
is unclear, since it uses cache maintenance by set/way to perform
the clean to PoU, which is a dubious practice to begin with. So
remove the declaration and all definitions.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <[email protected]>
Acked-by: Mark Rutland <[email protected]>
Reviewed-by: Leif Lindholm <[email protected]>
Modified Paths:
--------------
trunk/edk2/ArmPkg/Include/Library/ArmLib.h
trunk/edk2/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c
trunk/edk2/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h
trunk/edk2/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
trunk/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c
trunk/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.h
trunk/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
trunk/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
Modified: trunk/edk2/ArmPkg/Include/Library/ArmLib.h
===================================================================
--- trunk/edk2/ArmPkg/Include/Library/ArmLib.h 2015-11-09 13:25:50 UTC (rev
18751)
+++ trunk/edk2/ArmPkg/Include/Library/ArmLib.h 2015-11-09 13:26:11 UTC (rev
18752)
@@ -243,12 +243,6 @@
VOID
EFIAPI
-ArmCleanDataCacheToPoU (
- VOID
- );
-
-VOID
-EFIAPI
ArmInvalidateInstructionCache (
VOID
);
Modified: trunk/edk2/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c
===================================================================
--- trunk/edk2/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c 2015-11-09
13:25:50 UTC (rev 18751)
+++ trunk/edk2/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c 2015-11-09
13:26:11 UTC (rev 18752)
@@ -206,27 +206,7 @@
}
}
-
VOID
-AArch64PoUDataCacheOperation (
- IN AARCH64_CACHE_OPERATION DataCacheOperation
- )
-{
- UINTN SavedInterruptState;
-
- SavedInterruptState = ArmGetInterruptState ();
- ArmDisableInterrupts ();
-
- AArch64PerformPoUDataCacheOperation (DataCacheOperation);
-
- ArmDrainWriteBuffer ();
-
- if (SavedInterruptState) {
- ArmEnableInterrupts ();
- }
-}
-
-VOID
EFIAPI
ArmInvalidateDataCache (
VOID
@@ -255,13 +235,3 @@
ArmDrainWriteBuffer ();
AArch64DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
}
-
-VOID
-EFIAPI
-ArmCleanDataCacheToPoU (
- VOID
- )
-{
- ArmDrainWriteBuffer ();
- AArch64PoUDataCacheOperation (ArmCleanDataCacheEntryBySetWay);
-}
Modified: trunk/edk2/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h
===================================================================
--- trunk/edk2/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h 2015-11-09
13:25:50 UTC (rev 18751)
+++ trunk/edk2/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h 2015-11-09
13:26:11 UTC (rev 18752)
@@ -18,13 +18,7 @@
typedef VOID (*AARCH64_CACHE_OPERATION)(UINTN);
-
VOID
-AArch64PerformPoUDataCacheOperation (
- IN AARCH64_CACHE_OPERATION DataCacheOperation
- );
-
-VOID
AArch64AllDataCachesOperation (
IN AARCH64_CACHE_OPERATION DataCacheOperation
);
Modified: trunk/edk2/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
===================================================================
--- trunk/edk2/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S 2015-11-09
13:25:50 UTC (rev 18751)
+++ trunk/edk2/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S 2015-11-09
13:26:11 UTC (rev 18752)
@@ -40,7 +40,6 @@
GCC_ASM_EXPORT (ArmEnableBranchPrediction)
GCC_ASM_EXPORT (ArmDisableBranchPrediction)
GCC_ASM_EXPORT (AArch64AllDataCachesOperation)
-GCC_ASM_EXPORT (AArch64PerformPoUDataCacheOperation)
GCC_ASM_EXPORT (ArmDataMemoryBarrier)
GCC_ASM_EXPORT (ArmDataSynchronizationBarrier)
GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)
@@ -324,20 +323,7 @@
// right to ease the access to CSSELR and the
Set/Way operation.
cbz x3, L_Finished // No need to clean if LoC is 0
mov x10, #0 // Start clean at cache level 0
- b Loop1
-ASM_PFX(AArch64PerformPoUDataCacheOperation):
-// We can use regs 0-7 and 9-15 without having to save/restore.
-// Save our link register on the stack. - The stack must always be quad-word
aligned
- str x30, [sp, #-16]!
- mov x1, x0 // Save Function call in x1
- mrs x6, clidr_el1 // Read EL1 CLIDR
- and x3, x6, #0x38000000 // Mask out all but Point of Unification (PoU)
- lsr x3, x3, #26 // Left align cache level value - the level is
shifted by 1 to the
- // right to ease the access to CSSELR and the
Set/Way operation.
- cbz x3, L_Finished // No need to clean if LoC is 0
- mov x10, #0 // Start clean at cache level 0
-
Loop1:
add x2, x10, x10, lsr #1 // Work out 3x cachelevel for cache info
lsr x12, x6, x2 // bottom 3 bits are the Cache type for this
level
Modified: trunk/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c
===================================================================
--- trunk/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c 2015-11-09 13:25:50 UTC
(rev 18751)
+++ trunk/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c 2015-11-09 13:26:11 UTC
(rev 18752)
@@ -208,27 +208,7 @@
}
}
-
VOID
-ArmV7PoUDataCacheOperation (
- IN ARM_V7_CACHE_OPERATION DataCacheOperation
- )
-{
- UINTN SavedInterruptState;
-
- SavedInterruptState = ArmGetInterruptState ();
- ArmDisableInterrupts ();
-
- ArmV7PerformPoUDataCacheOperation (DataCacheOperation);
-
- ArmDrainWriteBuffer ();
-
- if (SavedInterruptState) {
- ArmEnableInterrupts ();
- }
-}
-
-VOID
EFIAPI
ArmInvalidateDataCache (
VOID
@@ -257,13 +237,3 @@
ArmDrainWriteBuffer ();
ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
}
-
-VOID
-EFIAPI
-ArmCleanDataCacheToPoU (
- VOID
- )
-{
- ArmDrainWriteBuffer ();
- ArmV7PoUDataCacheOperation (ArmCleanDataCacheEntryBySetWay);
-}
Modified: trunk/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.h
===================================================================
--- trunk/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.h 2015-11-09 13:25:50 UTC
(rev 18751)
+++ trunk/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.h 2015-11-09 13:26:11 UTC
(rev 18752)
@@ -17,13 +17,7 @@
typedef VOID (*ARM_V7_CACHE_OPERATION)(UINT32);
-
VOID
-ArmV7PerformPoUDataCacheOperation (
- IN ARM_V7_CACHE_OPERATION DataCacheOperation
- );
-
-VOID
ArmV7AllDataCachesOperation (
IN ARM_V7_CACHE_OPERATION DataCacheOperation
);
Modified: trunk/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
===================================================================
--- trunk/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S 2015-11-09
13:25:50 UTC (rev 18751)
+++ trunk/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S 2015-11-09
13:26:11 UTC (rev 18752)
@@ -38,7 +38,6 @@
GCC_ASM_EXPORT (ArmSetLowVectors)
GCC_ASM_EXPORT (ArmSetHighVectors)
GCC_ASM_EXPORT (ArmV7AllDataCachesOperation)
-GCC_ASM_EXPORT (ArmV7PerformPoUDataCacheOperation)
GCC_ASM_EXPORT (ArmDataMemoryBarrier)
GCC_ASM_EXPORT (ArmDataSynchronizationBarrier)
GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)
@@ -268,55 +267,6 @@
ldmfd SP!, {r4-r12, lr}
bx LR
-ASM_PFX(ArmV7PerformPoUDataCacheOperation):
- stmfd SP!,{r4-r12, LR}
- mov R1, R0 @ Save Function call in R1
- mrc p15, 1, R6, c0, c0, 1 @ Read CLIDR
- ands R3, R6, #0x38000000 @ Mask out all but Level of Unification (LoU)
- mov R3, R3, LSR #26 @ Cache level value (naturally aligned)
- beq Finished2
- mov R10, #0
-
-Loop4:
- add R2, R10, R10, LSR #1 @ Work out 3xcachelevel
- mov R12, R6, LSR R2 @ bottom 3 bits are the Cache type for this
level
- and R12, R12, #7 @ get those 3 bits alone
- cmp R12, #2
- blt Skip2 @ no cache or only instruction cache at this
level
- mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register
(CSSELR) // OR in 1 for Instruction
- isb @ isb to sync the change to the CacheSizeID reg
- mrc p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR)
- and R2, R12, #0x7 @ extract the line length field
- add R2, R2, #4 @ add 4 for the line length offset (log2 16
bytes)
- ldr R4, =0x3FF
- ands R4, R4, R12, LSR #3 @ R4 is the max number on the way size (right
aligned)
- clz R5, R4 @ R5 is the bit position of the way size
increment
- ldr R7, =0x00007FFF
- ands R7, R7, R12, LSR #13 @ R7 is the max number of the index size
(right aligned)
-
-Loop5:
- mov R9, R4 @ R9 working copy of the max way size (right
aligned)
-
-Loop6:
- orr R0, R10, R9, LSL R5 @ factor in the way number and cache number
into R11
- orr R0, R0, R7, LSL R2 @ factor in the index number
-
- blx R1
-
- subs R9, R9, #1 @ decrement the way number
- bge Loop6
- subs R7, R7, #1 @ decrement the index
- bge Loop5
-Skip2:
- add R10, R10, #2 @ increment the cache number
- cmp R3, R10
- bgt Loop4
-
-Finished2:
- dsb
- ldmfd SP!, {r4-r12, lr}
- bx LR
-
ASM_PFX(ArmDataMemoryBarrier):
dmb
bx LR
Modified: trunk/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
===================================================================
--- trunk/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm 2015-11-09
13:25:50 UTC (rev 18751)
+++ trunk/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm 2015-11-09
13:26:11 UTC (rev 18752)
@@ -35,7 +35,6 @@
EXPORT ArmSetLowVectors
EXPORT ArmSetHighVectors
EXPORT ArmV7AllDataCachesOperation
- EXPORT ArmV7PerformPoUDataCacheOperation
EXPORT ArmDataMemoryBarrier
EXPORT ArmDataSynchronizationBarrier
EXPORT ArmInstructionSynchronizationBarrier
@@ -262,55 +261,6 @@
ldmfd SP!, {r4-r12, lr}
bx LR
-ArmV7PerformPoUDataCacheOperation
- stmfd SP!,{r4-r12, LR}
- mov R1, R0 ; Save Function call in R1
- mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR
- ands R3, R6, #&38000000 ; Mask out all but Level of Unification (LoU)
- mov R3, R3, LSR #26 ; Cache level value (naturally aligned)
- beq Finished2
- mov R10, #0
-
-Loop4
- add R2, R10, R10, LSR #1 ; Work out 3xcachelevel
- mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this
level
- and R12, R12, #7 ; get those 3 bits alone
- cmp R12, #2
- blt Skip2 ; no cache or only instruction cache at this
level
- mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register
(CSSELR) // OR in 1 for Instruction
- isb ; isb to sync the change to the CacheSizeID reg
- mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)
- and R2, R12, #&7 ; extract the line length field
- add R2, R2, #4 ; add 4 for the line length offset (log2 16
bytes)
- ldr R4, =0x3FF
- ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right
aligned)
- clz R5, R4 ; R5 is the bit position of the way size
increment
- ldr R7, =0x00007FFF
- ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size
(right aligned)
-
-Loop5
- mov R9, R4 ; R9 working copy of the max way size (right
aligned)
-
-Loop6
- orr R0, R10, R9, LSL R5 ; factor in the way number and cache number
into R11
- orr R0, R0, R7, LSL R2 ; factor in the index number
-
- blx R1
-
- subs R9, R9, #1 ; decrement the way number
- bge Loop6
- subs R7, R7, #1 ; decrement the index
- bge Loop5
-Skip2
- add R10, R10, #2 ; increment the cache number
- cmp R3, R10
- bgt Loop4
-
-Finished2
- dsb
- ldmfd SP!, {r4-r12, lr}
- bx LR
-
ArmDataMemoryBarrier
dmb
bx LR
------------------------------------------------------------------------------
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