Revision: 18755
http://sourceforge.net/p/edk2/code/18755
Author: abiesheuvel
Date: 2015-11-09 13:27:15 +0000 (Mon, 09 Nov 2015)
Log Message:
-----------
ArmPkg/ArmLib: move cache maintenance sync barriers out of loop
There is no need to issue a full data synchronization barrier and an
instruction synchronization barrier after each and every set/way or
MVA cache maintenance operation. For the set/way case, we can simply
remove them, since the set/way outer loop already issues the required
barriers after completing its traversal over all the cache levels.
For the MVA case, move the data synchronization barrier out of the
loop, and add the instruction synchronization barrier to the I-cache
invalidation by MVA routine.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <[email protected]>
Reviewed-by: Mark Rutland <[email protected]>
Reviewed-by: Leif Lindholm <[email protected]>
Modified Paths:
--------------
trunk/edk2/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
trunk/edk2/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
trunk/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
trunk/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
Modified:
trunk/edk2/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
===================================================================
--- trunk/edk2/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
2015-11-09 13:26:52 UTC (rev 18754)
+++ trunk/edk2/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
2015-11-09 13:27:15 UTC (rev 18755)
@@ -35,6 +35,7 @@
LineOperation(AlignedAddress);
AlignedAddress += ArmCacheLineLength;
}
+ ArmDataSynchronizationBarrier ();
}
VOID
Modified: trunk/edk2/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
===================================================================
--- trunk/edk2/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S 2015-11-09
13:26:52 UTC (rev 18754)
+++ trunk/edk2/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S 2015-11-09
13:27:15 UTC (rev 18755)
@@ -65,43 +65,31 @@
ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
dc ivac, x0 // Invalidate single data cache line
- dsb sy
- isb
ret
ASM_PFX(ArmCleanDataCacheEntryByMVA):
dc cvac, x0 // Clean single data cache line
- dsb sy
- isb
ret
ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
dc civac, x0 // Clean and invalidate single data cache line
- dsb sy
- isb
ret
ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
dc isw, x0 // Invalidate this line
- dsb sy
- isb
ret
ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
dc cisw, x0 // Clean and Invalidate this line
- dsb sy
- isb
ret
ASM_PFX(ArmCleanDataCacheEntryBySetWay):
dc csw, x0 // Clean this line
- dsb sy
- isb
ret
Modified: trunk/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
===================================================================
--- trunk/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S 2015-11-09
13:26:52 UTC (rev 18754)
+++ trunk/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S 2015-11-09
13:27:15 UTC (rev 18755)
@@ -62,42 +62,30 @@
ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
- dsb
- isb
bx lr
ASM_PFX(ArmCleanDataCacheEntryByMVA):
mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
- dsb
- isb
bx lr
ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line
- dsb
- isb
bx lr
ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line
- dsb
- isb
bx lr
ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line
- dsb
- isb
bx lr
ASM_PFX(ArmCleanDataCacheEntryBySetWay):
mcr p15, 0, r0, c7, c10, 2 @ Clean this line
- dsb
- isb
bx lr
ASM_PFX(ArmInvalidateInstructionCache):
Modified: trunk/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
===================================================================
--- trunk/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm 2015-11-09
13:26:52 UTC (rev 18754)
+++ trunk/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm 2015-11-09
13:27:15 UTC (rev 18755)
@@ -62,42 +62,30 @@
ArmInvalidateDataCacheEntryByMVA
mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
- dsb
- isb
bx lr
ArmCleanDataCacheEntryByMVA
mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
- dsb
- isb
bx lr
ArmCleanInvalidateDataCacheEntryByMVA
mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
- dsb
- isb
bx lr
ArmInvalidateDataCacheEntryBySetWay
mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
- dsb
- isb
bx lr
ArmCleanInvalidateDataCacheEntryBySetWay
mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
- dsb
- isb
bx lr
ArmCleanDataCacheEntryBySetWay
mcr p15, 0, r0, c7, c10, 2 ; Clean this line
- dsb
- isb
bx lr
------------------------------------------------------------------------------
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