Revision: 18846
http://sourceforge.net/p/edk2/code/18846
Author: vanjeff
Date: 2015-11-17 05:10:45 +0000 (Tue, 17 Nov 2015)
Log Message:
-----------
UefiCpuPkg: SmmCpuFeaturesLib: Add MSR_SMM_FEATURE_CONTROL support
Add support for the reading and writing MSR_SMM_FEATURE_CONTROL
through the SmmCpuFeaturesIsSmmRegisterSupported(),
SmmCpuFeaturesGetSmmRegister(), and SmmCpuFeaturesSetSmmRegister()
functions. This MSR is supported if the Family/Model is 06_3C,
06_45, or 06_46.
(Sync patch r18690 from main trunk.)
Cc: "Yao, Jiewen" <[email protected]>
Cc: Jeff Fan <[email protected]>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <[email protected]>
Reviewed-by: "Yao, Jiewen" <[email protected]>
Revision Links:
--------------
http://sourceforge.net/p/edk2/code/18690
Modified Paths:
--------------
branches/UDK2015/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
Modified:
branches/UDK2015/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
===================================================================
--- branches/UDK2015/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
2015-11-17 05:10:07 UTC (rev 18845)
+++ branches/UDK2015/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
2015-11-17 05:10:45 UTC (rev 18846)
@@ -33,6 +33,7 @@
#define SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK 0x0A1
#define EFI_MSR_SMRR_MASK 0xFFFFF000
#define EFI_MSR_SMRR_PHYS_MASK_VALID BIT11
+#define SMM_FEATURES_LIB_SMM_FEATURE_CONTROL 0x4E0
//
// Set default value to assume SMRR is not supported
@@ -40,6 +41,11 @@
BOOLEAN mSmrrSupported = FALSE;
//
+// Set default value to assume MSR_SMM_FEATURE_CONTROL is not supported
+//
+BOOLEAN mSmmFeatureControlSupported = FALSE;
+
+//
// Set default value to assume IA-32 Architectural MSRs are used
//
UINT32 mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE;
@@ -127,6 +133,20 @@
//
// Intel(R) 64 and IA-32 Architectures Software Developer's Manual
+ // Volume 3C, Section 35.10.1 MSRs in 4th Generation Intel(R) Core(TM)
+ // Processor Family
+ //
+ // If CPU Family/Model is 06_3C, 06_45, or 06_46 then use 4th Generation
+ // Intel(R) Core(TM) Processor Family MSRs
+ //
+ if (FamilyId == 0x06) {
+ if (ModelId == 0x3C || ModelId == 0x45 || ModelId == 0x46) {
+ mSmmFeatureControlSupported = TRUE;
+ }
+ }
+
+ //
+ // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
// Volume 3C, Section 34.4.2 SMRAM Caching
// An IA-32 processor does not automatically write back and invalidate its
// caches before entering SMM or before exiting SMM. Because of this
behavior,
@@ -457,6 +477,9 @@
IN SMM_REG_NAME RegName
)
{
+ if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {
+ return TRUE;
+ }
return FALSE;
}
@@ -479,6 +502,9 @@
IN SMM_REG_NAME RegName
)
{
+ if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {
+ return AsmReadMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL);
+ }
return 0;
}
@@ -501,6 +527,9 @@
IN UINT64 Value
)
{
+ if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {
+ AsmWriteMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL, Value);
+ }
}
/**
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