Revision: 18903
http://sourceforge.net/p/edk2/code/18903
Author: abiesheuvel
Date: 2015-11-19 14:14:25 +0000 (Thu, 19 Nov 2015)
Log Message:
-----------
ArmPkg: correct TTBR1_EL1 settings in TCR_EL1
As EDK2 runs in an idmap, we do not use TTBR1_EL1, nor do we configure
it. TTBR1_EL1 may contain UNKNOWN values if it is not programmed since
reset.
Prior to enabling the MMU, we do not set TCR_EL1.EPD1, and hence the CPU
may make page table walks via TTBR1_EL1 at any time, potentially using
UNKNOWN values. This can result in a number of potential problems (e.g.
the CPU may load from MMIO registers as part of a page table walk).
Additionally, in the presence of Cortex-A57 erratum #822227, we must
program TCR_EL1.TG1 == 0b1x (e.g. 4KB granule) regardless of the value
of TCR_EL1.EPD1, to ensure that EDK2 can make forward progress under a
hypervisor which makes use of PAR_EL1.
This patch ensures that we program TCR_EL1.EPD1 and TCR_EL1.TG1 as above
to avoid these issues. TCR_EL1.TG1 is set to 4K for all targets, as any
CPU capable of running EDK2 must support this granule, and given
TCR_EL1.EPD1, programming the field is not detrimental in the absence of
the erratum.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Mark Rutland <[email protected]>
Reviewed-by: Ard Biesheuvel <[email protected]>
Modified Paths:
--------------
trunk/edk2/ArmPkg/Include/Chipset/AArch64Mmu.h
trunk/edk2/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
Modified: trunk/edk2/ArmPkg/Include/Chipset/AArch64Mmu.h
===================================================================
--- trunk/edk2/ArmPkg/Include/Chipset/AArch64Mmu.h 2015-11-19 08:37:03 UTC
(rev 18902)
+++ trunk/edk2/ArmPkg/Include/Chipset/AArch64Mmu.h 2015-11-19 14:14:25 UTC
(rev 18903)
@@ -108,6 +108,7 @@
#define TCR_PS_256TB (5 << 16)
#define TCR_TG0_4KB (0 << 14)
+#define TCR_TG1_4KB (2 << 30)
#define TCR_IPS_4GB (0ULL << 32)
#define TCR_IPS_64GB (1ULL << 32)
@@ -116,6 +117,7 @@
#define TCR_IPS_16TB (4ULL << 32)
#define TCR_IPS_256TB (5ULL << 32)
+#define TCR_EPD1 (1 << 23)
#define TTBR_ASID_FIELD (48)
#define TTBR_ASID_MASK (0xFF << TTBR_ASID_FIELD)
Modified: trunk/edk2/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
===================================================================
--- trunk/edk2/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c 2015-11-19
08:37:03 UTC (rev 18902)
+++ trunk/edk2/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c 2015-11-19
14:14:25 UTC (rev 18903)
@@ -628,7 +628,8 @@
return RETURN_UNSUPPORTED;
}
} else if (ArmReadCurrentEL () == AARCH64_EL1) {
- TCR = T0SZ | TCR_TG0_4KB;
+ // Due to Cortex-A57 erratum #822227 we must set TG1[1] == 1, regardless
of EPD1.
+ TCR = T0SZ | TCR_TG0_4KB | TCR_TG1_4KB | TCR_EPD1;
// Set the Physical Address Size using MaxAddress
if (MaxAddress < SIZE_4GB) {
------------------------------------------------------------------------------
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