Revision: 19068
http://sourceforge.net/p/edk2/code/19068
Author: lersek
Date: 2015-11-30 19:57:45 +0000 (Mon, 30 Nov 2015)
Log Message:
-----------
UefiCpuPkg/PiSmmCpu: Always set WP in CR0
So that we can use write-protection for code later.
It is REPOST.
It includes suggestion from Michael Kinney <[email protected]>:
- "For IA32 assembly, can we combine into a single OR instruction that
sets both page enable and WP?"
- "For X64, does it make sense to use single OR instruction instead of 2
BTS instructions as well?"
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <[email protected]>
Suggested-by: Michael Kinney <[email protected]>
Reviewed-by: Michael Kinney <[email protected]>
Tested-by: Laszlo Ersek <[email protected]>
Cc: "Fan, Jeff" <[email protected]>
Cc: "Kinney, Michael D" <[email protected]>
Cc: "Laszlo Ersek" <[email protected]>
Cc: "Paolo Bonzini" <[email protected]>
Modified Paths:
--------------
trunk/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
trunk/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
trunk/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S
trunk/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm
Modified: trunk/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
===================================================================
--- trunk/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S 2015-11-30
19:57:40 UTC (rev 19067)
+++ trunk/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S 2015-11-30
19:57:45 UTC (rev 19068)
@@ -123,7 +123,7 @@
L12: # as cr4.PGE is not set here,
refresh cr3
movl %eax, %cr4 # in PreModifyMtrrs() to flush TLB.
movl %cr0, %ebx
- orl $0x080000000, %ebx # enable paging
+ orl $0x080010000, %ebx # enable paging + WP
movl %ebx, %cr0
leal DSC_OFFSET(%edi),%ebx
movw DSC_DS(%ebx),%ax
Modified: trunk/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
===================================================================
--- trunk/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm 2015-11-30
19:57:40 UTC (rev 19067)
+++ trunk/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm 2015-11-30
19:57:45 UTC (rev 19068)
@@ -129,7 +129,7 @@
@@: ; as cr4.PGE is not set here, refresh
cr3
mov cr4, eax ; in PreModifyMtrrs() to flush TLB.
mov ebx, cr0
- or ebx, 080000000h ; enable paging
+ or ebx, 080010000h ; enable paging + WP
mov cr0, ebx
lea ebx, [edi + DSC_OFFSET]
mov ax, [ebx + DSC_DS]
Modified: trunk/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S
===================================================================
--- trunk/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S 2015-11-30 19:57:40 UTC
(rev 19067)
+++ trunk/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S 2015-11-30 19:57:45 UTC
(rev 19068)
@@ -144,7 +144,7 @@
orb $1,%ah
wrmsr
movq %cr0, %rbx
- btsl $31, %ebx
+ orl $0x080010000, %ebx # enable paging + WP
movq %rbx, %cr0
retf
LongMode: # long mode (64-bit code) starts here
Modified: trunk/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm
===================================================================
--- trunk/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm 2015-11-30
19:57:40 UTC (rev 19067)
+++ trunk/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm 2015-11-30
19:57:45 UTC (rev 19068)
@@ -140,7 +140,7 @@
or ah, 1
wrmsr
mov rbx, cr0
- bts ebx, 31
+ or ebx, 080010000h ; enable paging + WP
mov cr0, rbx
retf
@LongMode: ; long mode (64-bit code) starts here
------------------------------------------------------------------------------
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