Branch: refs/heads/master
Home: https://github.com/tianocore/edk2
Commit: 12460e227fa62d5b6c863f2167abcf5a6ca5a10b
https://github.com/tianocore/edk2/commit/12460e227fa62d5b6c863f2167abcf5a6ca5a10b
Author: Leahy, Leroy P <leroy.p.le...@intel.com>
Date: 2016-05-10 (Tue, 10 May 2016)
Changed paths:
A CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
A
CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
A
CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.uni
Log Message:
-----------
CorebootModulePkg: Add BaseSerialPortLib16550
Copy MdeModulePkg/Library/BaseSerialPortLib16550 revision
89ecd4cf8078aa946083cdcbf9af81ff29f8d9f5.
Change-Id: Ie2fd0123bdd7aaba4335afdb1cb017f3690455c6
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.le...@intel.com>
Reviewed-by: Prince Agyeman <prince.agye...@intel.com>
Commit: b08993bd13578b081f7c416efe932be6b73194b2
https://github.com/tianocore/edk2/commit/b08993bd13578b081f7c416efe932be6b73194b2
Author: Leahy, Leroy P <leroy.p.le...@intel.com>
Date: 2016-05-10 (Tue, 10 May 2016)
Changed paths:
M CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
M
CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
Log Message:
-----------
CorebootModulePkg/BaseSerialPortLib16550: Remove white-space
Remove trailing white space.
Change-Id: I73c3a3e1e55eec20b09443de1966573c97fa74f8
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.le...@intel.com>
Reviewed-by: Prince Agyeman <prince.agye...@intel.com>
Commit: bb0831670f11b710f36e1932d8ba83f1754f74dd
https://github.com/tianocore/edk2/commit/bb0831670f11b710f36e1932d8ba83f1754f74dd
Author: Leahy, Leroy P <leroy.p.le...@intel.com>
Date: 2016-05-10 (Tue, 10 May 2016)
Changed paths:
M CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
Log Message:
-----------
CorebootModulePkg/BaseSerialPortLib: Set DTR and RTS
Ensure communication between the host and the UEFI system running
CorebootPayloadPkg. In cases where the host has flow control enabled
and the serial connection is providing the flow control signals, the
host will not be able to send data to the UEFI system because DTR and
RTS are not present. The host may also discard all output data from
the UEFI system because DTR is not present. By setting DTR and RTS
in the UART initialization code this case works properly.
Change-Id: I393f57104d111472cafcae01d4e43d4ea837be3b
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.le...@intel.com>
Reviewed-by: Prince Agyeman <prince.agye...@intel.com>
Commit: a4fdb495dbf4bd6d741f9deb7db29986551ca8ea
https://github.com/tianocore/edk2/commit/a4fdb495dbf4bd6d741f9deb7db29986551ca8ea
Author: Leahy, Leroy P <leroy.p.le...@intel.com>
Date: 2016-05-10 (Tue, 10 May 2016)
Changed paths:
M CorebootModulePkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c
Log Message:
-----------
CorebootModulePkg/PciBusNoEnumerationDxe: Remove white space
Remove trailing white space from PciEnumeratorSupport.c.
Change-Id: Ia2f354151d46c09b140e2b42609d76fbbf8333f9
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.le...@intel.com>
Reviewed-by: Prince Agyeman <prince.agye...@intel.com>
Commit: deac23ab9678722c84c4ea0f70ff2bbbf04ff3aa
https://github.com/tianocore/edk2/commit/deac23ab9678722c84c4ea0f70ff2bbbf04ff3aa
Author: Leahy, Leroy P <leroy.p.le...@intel.com>
Date: 2016-05-10 (Tue, 10 May 2016)
Changed paths:
M CorebootModulePkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c
Log Message:
-----------
CorebootPayloadPkg/PciBusNoEnumerationDxe: Skip disabled devices
Skip non-bridge devices which are not enabled either for memory or I/O
access.
Change-Id: I1a39c69a8556b6b9cefd1a2bb191f7e0744ddfb0
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.le...@intel.com>
Reviewed-by: Prince Agyeman <prince.agye...@intel.com>
Commit: 24ca2f3507056e6a86cb0c0f088bba96cd117d71
https://github.com/tianocore/edk2/commit/24ca2f3507056e6a86cb0c0f088bba96cd117d71
Author: Leahy, Leroy P <leroy.p.le...@intel.com>
Date: 2016-05-10 (Tue, 10 May 2016)
Changed paths:
M CorebootModulePkg/Include/Coreboot.h
M CorebootModulePkg/Include/Library/CbParseLib.h
M CorebootModulePkg/Library/CbParseLib/CbParseLib.c
M CorebootPayloadPkg/Library/PlatformBdsLib/BdsPlatform.c
M CorebootPayloadPkg/Library/PlatformBdsLib/PlatformBdsLib.inf
M CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c
M CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf
Log Message:
-----------
CorebootPayloadPkg/PlatformBdsLib: Pass more serial parameters
Pass the serial port baudrate, register stride, input clock rate and
ID from coreboot to CorebootPayloadPkg.
Change-Id: I37111d23216e4effa2909337af7e8a6de36b61f7
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.le...@intel.com>
Reviewed-by: Prince Agyeman <prince.agye...@intel.com>
Compare: https://github.com/tianocore/edk2/compare/505e7fd5d07a...24ca2f350705------------------------------------------------------------------------------
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