Branch: refs/heads/master
  Home:   https://github.com/tianocore/edk2
  Commit: dbe10619bc443215477c5c0c4c949410bf68b1ec
      
https://github.com/tianocore/edk2/commit/dbe10619bc443215477c5c0c4c949410bf68b1ec
  Author: Feng Tian <feng.t...@intel.com>
  Date:   2016-09-21 (Wed, 21 Sep 2016)

  Changed paths:
    M MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c

  Log Message:
  -----------
  MdeModulePkg/XhciDxe:1ms delay before access MMIO reg during reset

Some XHCI host controllers require to have extra 1ms delay before
accessing any MMIO register during HC reset.

As this delay is not defined by XHCI spec, we use this workaround
to fix the issue.

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.t...@intel.com>
Reviewed-by: Star Zeng <star.z...@intel.com>


  Commit: 1f87985ab7958664a84da78095b5892f88acf3f1
      
https://github.com/tianocore/edk2/commit/1f87985ab7958664a84da78095b5892f88acf3f1
  Author: Feng Tian <feng.t...@intel.com>
  Date:   2016-09-21 (Wed, 21 Sep 2016)

  Changed paths:
    M MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c

  Log Message:
  -----------
  MdeModulePkg/XhciPei:1ms delay before access MMIO reg during reset

Some XHCI host controllers require to have extra 1ms delay before
accessing any MMIO register during HC reset.

As this delay is not defined by XHCI spec, we use this workaround
to fix the issue.

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.t...@intel.com>
Reviewed-by: Star Zeng <star.z...@intel.com>


Compare: https://github.com/tianocore/edk2/compare/7419aedd9313...1f87985ab795
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