Branch: refs/heads/master
Home: https://github.com/tianocore/edk2
Commit: 89f569ae8e759dc867009f396a516b7af5a3c0e7
https://github.com/tianocore/edk2/commit/89f569ae8e759dc867009f396a516b7af5a3c0e7
Author: Chasel Chiu <chasel.c...@intel.com>
Date: 2020-06-23 (Tue, 23 Jun 2020)
Changed paths:
M IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
M IntelFsp2Pkg/Include/FspEas/FspApi.h
M IntelFsp2Pkg/Tools/GenCfgOpt.py
Log Message:
-----------
IntelFsp2Pkg: Add FSP*_ARCH_UPD.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2781
Introduce FSPT_ARCH_UPD and FSPS_ARCH_UPD to support debug events
and multi-phase silicon initialization.
For backward compatibility the original structures are kept and
new ARCH_UPD structures will be included only when UPD header
revision equal or greater than 2.
GenCfgOpt script also updated to prevent from generating duplicate
FSPT_ARCH_UPD and FSPS_ARCH_UPD typedef structures.
Cc: Maurice Ma <maurice...@intel.com>
Cc: Nate DeSimone <nathaniel.l.desim...@intel.com>
Cc: Star Zeng <star.z...@intel.com>
Signed-off-by: Chasel Chiu <chasel.c...@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desim...@intel.com>
Commit: 1a992030522622c42aa063788b3276789c56c1e1
https://github.com/tianocore/edk2/commit/1a992030522622c42aa063788b3276789c56c1e1
Author: Chasel Chiu <chasel.c...@intel.com>
Date: 2020-06-23 (Tue, 23 Jun 2020)
Changed paths:
M
IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamInitData.c
Log Message:
-----------
IntelFsp2WrapperPkg: Add FSP*_ARCH_UPD.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2781
Provides sample code to include FSPT_ARCH_UPD initial values with
UPD header revision set to 2.
Cc: Maurice Ma <maurice...@intel.com>
Cc: Nate DeSimone <nathaniel.l.desim...@intel.com>
Cc: Star Zeng <star.z...@intel.com>
Signed-off-by: Chasel Chiu <chasel.c...@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desim...@intel.com>
Compare: https://github.com/tianocore/edk2/compare/00b8bf7eda00...1a9920305226
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