Branch: refs/heads/master
Home: https://github.com/tianocore/edk2
Commit: 60d8bb9f28f663e6ca58bc87c042fdd82f5607bd
https://github.com/tianocore/edk2/commit/60d8bb9f28f663e6ca58bc87c042fdd82f5607bd
Author: Ashraf Ali S <ashraf.al...@intel.com>
Date: 2021-09-16 (Thu, 16 Sep 2021)
Changed paths:
A UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.port80.raw
A UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.raw
A UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.serial.raw
R UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw
R UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.raw
R UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.serial.raw
M UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.inf
R UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.x64.port80.raw
R UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.x64.raw
R UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.x64.serial.raw
A UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector1G.inf
A UefiCpuPkg/ResetVector/Vtf0/Bin/X64/PageTable1G/ResetVector.x64.port80.raw
A UefiCpuPkg/ResetVector/Vtf0/Bin/X64/PageTable1G/ResetVector.x64.raw
A UefiCpuPkg/ResetVector/Vtf0/Bin/X64/PageTable1G/ResetVector.x64.serial.raw
A UefiCpuPkg/ResetVector/Vtf0/Bin/X64/PageTable2M/ResetVector.x64.port80.raw
A UefiCpuPkg/ResetVector/Vtf0/Bin/X64/PageTable2M/ResetVector.x64.raw
A UefiCpuPkg/ResetVector/Vtf0/Bin/X64/PageTable2M/ResetVector.x64.serial.raw
M UefiCpuPkg/ResetVector/Vtf0/Build.py
A UefiCpuPkg/ResetVector/Vtf0/PageTables.inc
M UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt
M UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
R UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm
A UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm
A UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm
M UefiCpuPkg/UefiCpuPkg.ci.yaml
Log Message:
-----------
UefiCpuPkg: VTF0 Linear-Address Translation to a 1-GByte Page till 512GB
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3473
X64 Reset Vector Code can access the memory range till 4GB using the
Linear-Address Translation to a 2-MByte Page, when user wants to use
more than 4G using 2M Page it will leads to use more number of Page
table entries. using the 1-GByte Page table user can use more than
4G Memory by reducing the page table entries using 1-GByte Page,
this patch attached can access memory range till 512GByte via Linear-
Address Translation to a 1-GByte Page.
Build Tool: if the nasm is not found it will throw Build errors like
FileNotFoundError: [WinError 2]The system cannot find the file specified
run the command wil try except block to get meaningful error message
Test Result: Tested in both Simulation environment and Hardware
both works fine without any issues.
Reviewed-by: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Cc: Debkumar De <debkumar...@intel.com>
Cc: Harry Han <harry....@intel.com>
Cc: Catharine West <catharine.w...@intel.com>
Cc: Sangeetha V <sangeeth...@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaga...@intel.com>
Cc: Sahil Dureja <sahil.dur...@intel.com>
Signed-off-by: Ashraf Ali S <ashraf.al...@intel.com>
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