Branch: refs/heads/master
Home: https://github.com/tianocore/edk2
Commit: de463163d9f6d3c5dc6b55ff35d1e5676e0e1b9f
https://github.com/tianocore/edk2/commit/de463163d9f6d3c5dc6b55ff35d1e5676e0e1b9f
Author: Gerd Hoffmann <kra...@redhat.com>
Date: 2022-02-28 (Mon, 28 Feb 2022)
Changed paths:
M OvmfPkg/AmdSev/AmdSevX64.fdf
Log Message:
-----------
OvmfPkg/AmdSev: reserve snp pages
The SNP patch series updated the OvmfPkgX64 build but forgot the AmdSev
variant, resulting in a broken OvmfSevMetadata table.
Fixes: cca9cd3dd6bf ("OvmfPkg: reserve CPUID page")
Fixes: 707c71a01b9d ("OvmfPkg: reserve SNP secrets page")
Signed-off-by: Gerd Hoffmann <kra...@redhat.com>
Reviewed-by: Brijesh Singh <brijesh.si...@amd.com>
Acked-by: Jiewen Yao <jiewen....@intel.com>
Commit: 63c50d3ff2854a76432b752af4f2a76f33ff1974
https://github.com/tianocore/edk2/commit/63c50d3ff2854a76432b752af4f2a76f33ff1974
Author: Brijesh Singh <brijesh.si...@amd.com>
Date: 2022-02-28 (Mon, 28 Feb 2022)
Changed paths:
M OvmfPkg/Include/WorkArea.h
M OvmfPkg/ResetVector/Ia32/AmdSev.asm
M OvmfPkg/ResetVector/Ia32/Flat32ToFlat64.asm
M OvmfPkg/ResetVector/ResetVector.nasmb
M OvmfPkg/Sec/AmdSev.c
Log Message:
-----------
OvmfPkg/ResetVector: cache the SEV status MSR value in workarea
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3582
In order to probe the SEV feature the BaseMemEncryptLib and Reset vector
reads the SEV_STATUS MSR. Cache the value on the first read in the
workarea. In the next patches the value saved in the workarea will
be used by the BaseMemEncryptLib. This not only eliminates the extra
MSR reads it also helps cleaning up the code in BaseMemEncryptLib.
Cc: Min Xu <min.m...@intel.com>
Cc: Jiewen Yao <jiewen....@intel.com>
Cc: Tom Lendacky <thomas.lenda...@amd.com>
Cc: Jordan Justen <jordan.l.jus...@intel.com>
Cc: Ard Biesheuvel <ardb+tianoc...@kernel.org>
Cc: Erdem Aktas <erdemak...@google.com>
Cc: Gerd Hoffmann <kra...@redhat.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Signed-off-by: Brijesh Singh <brijesh.si...@amd.com>
Acked-by: Jiewen Yao <jiewen....@intel.com>
Commit: f1d1c337e7c0575da7fd248b2dd9cffc755940df
https://github.com/tianocore/edk2/commit/f1d1c337e7c0575da7fd248b2dd9cffc755940df
Author: Brijesh Singh <brijesh.si...@amd.com>
Date: 2022-02-28 (Mon, 28 Feb 2022)
Changed paths:
M OvmfPkg/Library/BaseMemEncryptSevLib/DxeMemEncryptSevLib.inf
M OvmfPkg/Library/BaseMemEncryptSevLib/DxeMemEncryptSevLibInternal.c
M OvmfPkg/Library/BaseMemEncryptSevLib/PeiMemEncryptSevLib.inf
M OvmfPkg/Library/BaseMemEncryptSevLib/PeiMemEncryptSevLibInternal.c
M OvmfPkg/Library/BaseMemEncryptSevLib/SecMemEncryptSevLib.inf
M OvmfPkg/Library/BaseMemEncryptSevLib/SecMemEncryptSevLibInternal.c
Log Message:
-----------
OvmfPkg/BaseMemEncryptLib: use the SEV_STATUS MSR value from workarea
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3582
Improve the MemEncryptSev{Es,Snp}IsEnabled() to use the SEV_STATUS MSR
value saved in the workarea. Since workarea is valid until the PEI phase,
so, for the Dxe phase use the PcdConfidentialComputingGuestAttr to
determine which SEV technology is enabled.
Cc: Min Xu <min.m...@intel.com>
Cc: Jiewen Yao <jiewen....@intel.com>
Cc: Tom Lendacky <thomas.lenda...@amd.com>
Cc: Jordan Justen <jordan.l.jus...@intel.com>
Cc: Ard Biesheuvel <ardb+tianoc...@kernel.org>
Cc: Erdem Aktas <erdemak...@google.com>
Cc: Gerd Hoffmann <kra...@redhat.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Signed-off-by: Brijesh Singh <brijesh.si...@amd.com>
Acked-by: Jiewen Yao <jiewen....@intel.com>
Compare: https://github.com/tianocore/edk2/compare/54cddc3ad4b3...f1d1c337e7c0
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