Branch: refs/heads/master
Home: https://github.com/tianocore/edk2
Commit: 83d5871184d1e09332565bfc939e5fc8354b5b79
https://github.com/tianocore/edk2/commit/83d5871184d1e09332565bfc939e5fc8354b5b79
Author: Dun Tan <dun....@intel.com>
Date: 2022-08-15 (Mon, 15 Aug 2022)
Changed paths:
M UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
Log Message:
-----------
UefiCpuPkg/PiSmmCpuDxeSmm: Add a new mIsShadowStack flag
This patch is code refactoring and doesn't change any functionality.
Add a new mIsShadowStack flag to identify whether current memory is
shadow stack. Previous smm code logic regards a RO range as shadow
stack and set the dirty bit in corresponding page table entry if
mInternalCr3 is not 0, which may be confusing.
Signed-off-by: Dun Tan <dun....@intel.com>
Cc: Eric Dong <eric.d...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Commit: 7b4754904efd5503d191f034ef17e982ceb65962
https://github.com/tianocore/edk2/commit/7b4754904efd5503d191f034ef17e982ceb65962
Author: Dun Tan <dun....@intel.com>
Date: 2022-08-15 (Mon, 15 Aug 2022)
Changed paths:
M UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c
M UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
M UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
M UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
Log Message:
-----------
UefiCpuPkg/PiSmmCpuDxeSmm: Remove mInternalCr3 in PiSmmCpuDxeSmm
This patch is code refactoring and doesn't change any functionality.
Remove mInternalCr3 in PiSmmCpuDxe pagetable related code. In previous
code, mInternalCr3 is used to pass address of page table which is
different from Cr3 register in different level of SetMemoryAttributes
function. Now remove it and pass the page table base address from the
root function parameter to simplify the code logic.
Signed-off-by: Dun Tan <dun....@intel.com>
Cc: Eric Dong <eric.d...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Commit: 62391b4ce962095018bffed55422ae4ba6ef94d6
https://github.com/tianocore/edk2/commit/62391b4ce962095018bffed55422ae4ba6ef94d6
Author: Dun Tan <dun....@intel.com>
Date: 2022-08-15 (Mon, 15 Aug 2022)
Changed paths:
M MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
Log Message:
-----------
MdeModulePkg/DxeIpl: Remove clearing CR0.WP when protecting pagetable
Remove clearing CR0.WP when marking the memory used for page table
as read-only in the page table itself created by DxeIpl. This page
table address is written to Cr3 after these protection steps. Till
this, the memory used for page table is always RW.
Signed-off-by: Dun Tan <dun....@intel.com>
Cc: Dandan Bi <dandan...@intel.com>
Cc: Liming Gao <gaolim...@byosoft.com.cn>
Reviewed-by: Ray Ni <ray...@intel.com>
Commit: 803ed060ee2b22cc136ae97308d494a9d6716947
https://github.com/tianocore/edk2/commit/803ed060ee2b22cc136ae97308d494a9d6716947
Author: Dun Tan <dun....@intel.com>
Date: 2022-08-15 (Mon, 15 Aug 2022)
Changed paths:
M UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
Log Message:
-----------
UefiPayloadPkg: Remove clearing CR0.WP when protecting pagetable
Remove clearing CR0.WP when marking the memory used for page table
as read-only in the page table itself created by UefiPayloadEntry.
This page table address is written to Cr3 after these protection
steps. Till this, the memory used for page table is always RW.
Signed-off-by: Dun Tan <dun....@intel.com>
Reviewed-by: Guo Dong <guo.d...@intel.com>
Cc: Maurice Ma <maurice...@intel.com>
Cc: Benjamin You <benjamin....@intel.com>
Cc: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Ray Ni <ray...@intel.com>
Compare: https://github.com/tianocore/edk2/compare/74f44d920a28...803ed060ee2b
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