Branch: refs/heads/master
  Home:   https://github.com/tianocore/edk2
  Commit: 367604b2f49f1b7517756a4ecab426f5308ba7fb
      
https://github.com/tianocore/edk2/commit/367604b2f49f1b7517756a4ecab426f5308ba7fb
  Author: Liu, Zhiguang <zhiguang....@intel.com>
  Date:   2022-08-31 (Wed, 31 Aug 2022)

  Changed paths:
    M UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm

  Log Message:
  -----------
  UefiCpuPkg/MpInitLib: Fix potential issue when IDT table is at above 4G

Currently, when waking up AP, IDT table of AP will be set in 16 bit code,
and assume the IDT table base is 32 bit. However, the IDT table is created
by BSP. Issue will happen if the BSP allocates memory above 4G for BSP's
IDT table. Moreover, even the IDT table location is below 4G, the handler
function inside the IDT table is 64 bit, and it won't take effect until
CPU transfers to 64 bit long mode. There is no benefit to set IDT table in
such an early phase.
To avoid such issue, this patch moves the LIDT instruction into 64 bit
code.

Cc: Eric Dong <eric.d...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang....@intel.com>


  Commit: 76ec17526b7ebd0893f8e2e27ee4e4baf017eeef
      
https://github.com/tianocore/edk2/commit/76ec17526b7ebd0893f8e2e27ee4e4baf017eeef
  Author: Wu, Jiaxin <jiaxin...@intel.com>
  Date:   2022-08-31 (Wed, 31 Aug 2022)

  Changed paths:
    M UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
    M UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c
    M UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
    M UefiCpuPkg/Library/SmmCpuFeaturesLib/StandaloneMmCpuFeaturesLib.inf
    M UefiCpuPkg/UefiCpuPkg.dec
    M UefiCpuPkg/UefiCpuPkg.uni

  Log Message:
  -----------
  UefiCpuPkg: Add PCD to control SMRR enable & SmmFeatureControl support

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3962

Two SMM variables (mSmrrSupported & mSmmFeatureControlSupported) are global
variables, they control whether the SMRR and SMM Feature Control MSR will
be restored respectively.
To avoid the TOCTOU, add PCD to control SMRR & SmmFeatureControl enable.

Cc: Eric Dong <eric.d...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Cc: Star Zeng <star.z...@intel.com>
Cc: Michael D Kinney <michael.d.kin...@intel.com>
Signed-off-by: Jiaxin Wu <jiaxin...@intel.com>


  Commit: d1abb876f4846a22bfc72e10c1aea2b5c847f90c
      
https://github.com/tianocore/edk2/commit/d1abb876f4846a22bfc72e10c1aea2b5c847f90c
  Author: Liu, Zhiguang <zhiguang....@intel.com>
  Date:   2022-08-31 (Wed, 31 Aug 2022)

  Changed paths:
    M UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm
    M UefiCpuPkg/Library/MpInitLib/MpLib.c
    M UefiCpuPkg/Library/MpInitLib/MpLib.h
    M UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm

  Log Message:
  -----------
  UefiCpuPkg/MpInitLib: Simplify logic in SwitchBsp

When switch bsp, old bsp and new bsp put CR0/CR4 into stack, and put IDT
and GDT register into a structure. After they exchange their stack, they
restore these registers. This logic is now implemented by assembly code.
This patch aims to reuse (Save/Restore)VolatileRegisters function to
replace such assembly code for better code readability.

Cc: Eric Dong <eric.d...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang....@intel.com>


  Commit: 76cf3d35e6cc20140e50b299aa7162ced4acef59
      
https://github.com/tianocore/edk2/commit/76cf3d35e6cc20140e50b299aa7162ced4acef59
  Author: Liu, Zhiguang <zhiguang....@intel.com>
  Date:   2022-08-31 (Wed, 31 Aug 2022)

  Changed paths:
    M UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
    M UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
    M UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
    M UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c
    M UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
    M UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
    M UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
    M 
UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHandlerLib.inf

  Log Message:
  -----------
  UefiCpuPkg: Simplify the implementation when separate exception stacks

The API of InitializeSeparateExceptionStacks is just changed before, and
makes the struct CPU_EXCEPTION_INIT_DATA an internal definition.
Furthermore, we can even remove the struct to make core simpler.

Cc: Eric Dong <eric.d...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang....@intel.com>


  Commit: 9ab2b34dd4f7e5cc6170ff812b0a07d58e5510b6
      
https://github.com/tianocore/edk2/commit/9ab2b34dd4f7e5cc6170ff812b0a07d58e5510b6
  Author: Yuanhao Xie <yuanhao....@intel.com>
  Date:   2022-08-31 (Wed, 31 Aug 2022)

  Changed paths:
    M UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm
    M UefiCpuPkg/Library/MpInitLib/MpLib.c
    M UefiCpuPkg/Library/MpInitLib/MpLib.h
    M UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
    M UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm

  Log Message:
  -----------
  UefiCpuPkg: Use Top of each AP's stack to save CpuMpData

To remove the dependency of CPU register, 4/8 byte at the top of the
stack is occupied for CpuMpData. BIST information is also taken care
here. This modification is only for PEI phase, since in DXE phase
CpuMpData is accessed via global variable.

Signed-off-by: Yuanhao Xie <yuanhao....@intel.com>
Cc: Eric Dong <eric.d...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>


  Commit: 4b7bd4c591a81a290b31e9d1a94c4b8be787989e
      
https://github.com/tianocore/edk2/commit/4b7bd4c591a81a290b31e9d1a94c4b8be787989e
  Author: Liu, Zhiguang <zhiguang....@intel.com>
  Date:   2022-08-31 (Wed, 31 Aug 2022)

  Changed paths:
    M UefiCpuPkg/CpuDxe/CpuMp.c
    M UefiCpuPkg/CpuMpPei/CpuMpPei.c

  Log Message:
  -----------
  UefiCpuPkg: Enhance logic in InitializeMpExceptionStackSwitchHandlers

Parallelly run the function to SeparateExceptionStacks for all CPUs and
allocate buffers together for better performance.

Cc: Eric Dong <eric.d...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang....@intel.com>


Compare: https://github.com/tianocore/edk2/compare/3c06953fd76c...4b7bd4c591a8


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