Branch: refs/heads/master
Home: https://github.com/tianocore/edk2
Commit: 01c2fb0d2260d4de898e4e91e48770ffa5510153
https://github.com/tianocore/edk2/commit/01c2fb0d2260d4de898e4e91e48770ffa5510153
Author: Matt DeVillier <matt.devill...@gmail.com>
Date: 2022-12-21 (Wed, 21 Dec 2022)
Changed paths:
M MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
Log Message:
-----------
MdeModulePkg/XhciDxe/Xhci: Don't check for invalid PSIV
PSID matching relies on comparing the PSIV against the PortSpeed
value. This patch stops edk2 from checking for a PSIV of 0, as it
is not valid; this reduces the number of register access by
approximately 6 per second.
Cc: Hao A Wu <hao.a...@intel.com>
Cc: Ray Ni <ray...@intel.com>
Signed-off-by: Matt DeVillier <matt.devill...@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Hao A Wu <hao.a...@intel.com>
Commit: ec25e904c7da70302f2725e2005e3762f1ae891e
https://github.com/tianocore/edk2/commit/ec25e904c7da70302f2725e2005e3762f1ae891e
Author: Sean Rhodes <sean@starlabs.systems>
Date: 2022-12-21 (Wed, 21 Dec 2022)
Changed paths:
M MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
M MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
M MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
Log Message:
-----------
MdeModulePkg/Bus/Pci/XhciDxe: Check port is compatible before getting PSIV
On some platforms, including Sky Lake and Kaby Lake, the PSIV (Protocol
Speed ID Value) indices are shared between Protocol Speed ID DWORD' in
the extended capabilities registers for both USB2 (Full Speed) and USB3
(Super Speed).
An example can be found below:
XhcCheckUsbPortSpeedUsedPsic: checking for USB2 ext caps
XhciPsivGetPsid: found 3 PSID entries
XhciPsivGetPsid: looking for port speed 1
XhciPsivGetPsid: PSIV 1 PSIE 2 PLT 0 PSIM 12
XhciPsivGetPsid: PSIV 2 PSIE 1 PLT 0 PSIM 1500
XhciPsivGetPsid: PSIV 3 PSIE 2 PLT 0 PSIM 480
XhcCheckUsbPortSpeedUsedPsic: checking for USB3 ext caps
XhciPsivGetPsid: found 3 PSID entries
XhciPsivGetPsid: looking for port speed 1
XhciPsivGetPsid: PSIV 1 PSIE 3 PLT 0 PSIM 5
XhciPsivGetPsid: PSIV 2 PSIE 3 PLT 0 PSIM 10
XhciPsivGetPsid: PSIV 34 PSIE 2 PLT 0 PSIM 1248
The result is edk2 detecting USB2 devices as USB3 devices, which
consequently causes enumeration to fail.
To avoid incorrect detection, check the Compatible Port Offset to find
the starting Port of Root Hubs that support the protocol.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Hao A Wu <hao.a...@intel.com>
Compare: https://github.com/tianocore/edk2/compare/3f378450dfaf...ec25e904c7da
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