Branch: refs/heads/master
Home: https://github.com/tianocore/edk2
Commit: 8aeb405466043c7e9ff9fb9a9b65b559094851da
https://github.com/tianocore/edk2/commit/8aeb405466043c7e9ff9fb9a9b65b559094851da
Author: Sunil V L <suni...@ventanamicro.com>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
A MdePkg/Include/Register/RiscV64/RiscVEncoding.h
A MdePkg/Include/Register/RiscV64/RiscVImpl.h
Log Message:
-----------
MdePkg/Register: Add register definition header files for RISC-V
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
Add register definitions and access routines for RISC-V. These
headers are leveraged from opensbi repo.
Cc: Daniel Schaefer <g...@danielschaefer.me>
Cc: Michael D Kinney <michael.d.kin...@intel.com>
Cc: Liming Gao <gaolim...@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang....@intel.com>
Signed-off-by: Sunil V L <suni...@ventanamicro.com>
Acked-by: Abner Chang <abner.ch...@amd.com>
Reviewed-by: Andrei Warkentin <andrei.warken...@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kin...@intel.com>
Commit: 550f196e823a9f857e0313e632d89b6653946f88
https://github.com/tianocore/edk2/commit/550f196e823a9f857e0313e632d89b6653946f88
Author: Sunil V L <suni...@ventanamicro.com>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
M MdePkg/Include/Library/BaseLib.h
M MdePkg/Library/BaseLib/BaseLib.inf
A MdePkg/Library/BaseLib/RiscV64/CpuScratch.S
A MdePkg/Library/BaseLib/RiscV64/ReadTimer.S
M MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S
A MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S
Log Message:
-----------
MdePkg/BaseLib: RISC-V: Add few more helper functions
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
Few of the basic helper functions required for any
RISC-V CPU were added in edk2-platforms. To support
qemu virt, they need to be added in BaseLib.
Cc: Michael D Kinney <michael.d.kin...@intel.com>
Cc: Liming Gao <gaolim...@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang....@intel.com>
Cc: Daniel Schaefer <g...@danielschaefer.me>
Signed-off-by: Sunil V L <suni...@ventanamicro.com>
Acked-by: Abner Chang <abner.ch...@amd.com>
Reviewed-by: Andrei Warkentin <andrei.warken...@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kin...@intel.com>
Commit: 76e956547eafc88a46c7620d0fb128d4e10b1c64
https://github.com/tianocore/edk2/commit/76e956547eafc88a46c7620d0fb128d4e10b1c64
Author: Sunil V L <suni...@ventanamicro.com>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
A MdePkg/Include/Library/BaseRiscVSbiLib.h
A MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.c
A MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf
A MdePkg/Library/BaseRiscVSbiLib/RiscVSbiEcall.S
M MdePkg/MdePkg.dec
M MdePkg/MdePkg.dsc
Log Message:
-----------
MdePkg: Add BaseRiscVSbiLib Library for RISC-V
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
This library is required to make SBI ecalls from the S-mode EDK2.
This is mostly copied from
edk2-platforms/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib
Cc: Michael D Kinney <michael.d.kin...@intel.com>
Cc: Liming Gao <gaolim...@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang....@intel.com>
Signed-off-by: Sunil V L <suni...@ventanamicro.com>
Acked-by: Abner Chang <abner.ch...@amd.com>
Reviewed-by: Andrei Warkentin <andrei.warken...@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kin...@intel.com>
Commit: d6017bca19c4c716c5c672e8de2f67658184b6f2
https://github.com/tianocore/edk2/commit/d6017bca19c4c716c5c672e8de2f67658184b6f2
Author: Sunil V L <suni...@ventanamicro.com>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
A UefiCpuPkg/Include/Protocol/RiscVBootProtocol.h
M UefiCpuPkg/UefiCpuPkg.dec
Log Message:
-----------
UefiCpuPkg: Add RISCV_EFI_BOOT_PROTOCOL related definitions
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
RISC-V UEFI based platforms need to support RISCV_EFI_BOOT_PROTOCOL.
Add this protocol GUID definition and the header file required.
Cc: Eric Dong <eric.d...@intel.com>
Cc: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Cc: Daniel Schaefer <g...@danielschaefer.me>
Cc: Gerd Hoffmann <kra...@redhat.com>
Signed-off-by: Sunil V L <suni...@ventanamicro.com>
Acked-by: Abner Chang <abner.ch...@amd.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schucha...@canonical.com>
Reviewed-by: Andrei Warkentin <andrei.warken...@intel.com>
Acked-by: Ray Ni <ray...@intel.com>
Commit: cbac2c74e803af7c6af1607d503906e3b2c46a2a
https://github.com/tianocore/edk2/commit/cbac2c74e803af7c6af1607d503906e3b2c46a2a
Author: Sunil V L <suni...@ventanamicro.com>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
A
UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.inf
A
UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.uni
A
UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/CpuExceptionHandlerLib.c
A
UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/CpuExceptionHandlerLib.h
A
UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/SupervisorTrapHandler.S
M UefiCpuPkg/UefiCpuPkg.dsc
Log Message:
-----------
UefiCpuPkg: Add BaseRiscV64CpuExceptionHandlerLib
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
Add Cpu Exception Handler library for RISC-V. This is copied
from edk2-platforms/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib
Cc: Eric Dong <eric.d...@intel.com>
Cc: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Cc: Daniel Schaefer <g...@danielschaefer.me>
Cc: Abner Chang <abner.ch...@amd.com>
Cc: Gerd Hoffmann <kra...@redhat.com>
Signed-off-by: Sunil V L <suni...@ventanamicro.com>
Acked-by: Abner Chang <abner.ch...@amd.com>
Reviewed-by: Andrei Warkentin <andrei.warken...@intel.com>
Acked-by: Ray Ni <ray...@intel.com>
Commit: 705c3469b543a8907499a3cad30aa256ae8a40c5
https://github.com/tianocore/edk2/commit/705c3469b543a8907499a3cad30aa256ae8a40c5
Author: Sunil V L <suni...@ventanamicro.com>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
A UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf
A UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.uni
A UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c
M UefiCpuPkg/UefiCpuPkg.dsc
Log Message:
-----------
UefiCpuPkg: Add BaseRiscV64CpuTimerLib library
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
Add the RISC-V instance of the TimerLib.
This is mostly copied from
edk2-platforms/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib
Cc: Eric Dong <eric.d...@intel.com>
Cc: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Cc: Daniel Schaefer <g...@danielschaefer.me>
Cc: Abner Chang <abner.ch...@amd.com>
Cc: Gerd Hoffmann <kra...@redhat.com>
Signed-off-by: Sunil V L <suni...@ventanamicro.com>
Acked-by: Abner Chang <abner.ch...@amd.com>
Reviewed-by: Andrei Warkentin <andrei.warken...@intel.com>
Acked-by: Ray Ni <ray...@intel.com>
Commit: 98fa877efd4fbdbddb532efe5ada5ca4aee67b85
https://github.com/tianocore/edk2/commit/98fa877efd4fbdbddb532efe5ada5ca4aee67b85
Author: Sunil V L <suni...@ventanamicro.com>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
A UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
A UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.uni
A UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64Extra.uni
A UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
A UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
M UefiCpuPkg/UefiCpuPkg.dsc
Log Message:
-----------
UefiCpuPkg: Add CpuTimerDxeRiscV64 module
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
This DXE module initializes the timer interrupt handler
and installs the Arch Timer protocol.
Cc: Eric Dong <eric.d...@intel.com>
Cc: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Cc: Daniel Schaefer <g...@danielschaefer.me>
Cc: Gerd Hoffmann <kra...@redhat.com>
Signed-off-by: Sunil V L <suni...@ventanamicro.com>
Acked-by: Abner Chang <abner.ch...@amd.com>
Reviewed-by: Andrei Warkentin <andrei.warken...@intel.com>
Acked-by: Ray Ni <ray...@intel.com>
Commit: c27cdc941d67afa1f15e718aee8557f6875619fd
https://github.com/tianocore/edk2/commit/c27cdc941d67afa1f15e718aee8557f6875619fd
Author: Sunil V L <suni...@ventanamicro.com>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
A UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
A UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
A UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
A UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.uni
A UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64Extra.uni
M UefiCpuPkg/UefiCpuPkg.dsc
Log Message:
-----------
UefiCpuPkg: Add CpuDxeRiscV64 module
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
This is copied from
edk2-platforms/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe
and added the RISCV_EFI_BOOT_PROTOCOL support.
Cc: Eric Dong <eric.d...@intel.com>
Cc: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Cc: Daniel Schaefer <g...@danielschaefer.me>
Cc: Gerd Hoffmann <kra...@redhat.com>
Signed-off-by: Sunil V L <suni...@ventanamicro.com>
Acked-by: Abner Chang <abner.ch...@amd.com>
Reviewed-by: Andrei Warkentin <andrei.warken...@intel.com>
Commit: a7dec790dc11427abc841d5a938df3319aad07fb
https://github.com/tianocore/edk2/commit/a7dec790dc11427abc841d5a938df3319aad07fb
Author: Sunil V L <suni...@ventanamicro.com>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
M UefiCpuPkg/UefiCpuPkg.ci.yaml
Log Message:
-----------
UefiCpuPkg/UefiCpuPkg.ci.yaml: Ignore RISC-V file
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
RISC-V register names do not follow the EDK2 formatting.
So, add it to ignore list for now.
Cc: Eric Dong <eric.d...@intel.com>
Cc: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Cc: Gerd Hoffmann <kra...@redhat.com>
Signed-off-by: Sunil V L <suni...@ventanamicro.com>
Acked-by: Abner Chang <abner.ch...@amd.com>
Reviewed-by: Andrei Warkentin <andrei.warken...@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kin...@intel.com>
Acked-by: Ray Ni <ray...@intel.com>
Commit: 09cd17b0deef4920a1845f70b0e4859f57726e6a
https://github.com/tianocore/edk2/commit/09cd17b0deef4920a1845f70b0e4859f57726e6a
Author: Sunil V L <suni...@ventanamicro.com>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
M ArmVirtPkg/ArmVirtPkg.dec
R ArmVirtPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.c
R ArmVirtPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf
M OvmfPkg/OvmfPkg.dec
A OvmfPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.c
A OvmfPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf
Log Message:
-----------
ArmVirtPkg/PlatformHasAcpiDtDxe: Move to OvmfPkg
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
This module is required by other architectures like RISC-V.
Hence, move this to OvmfPkg.
Cc: Ard Biesheuvel <ardb+tianoc...@kernel.org>
Cc: Jiewen Yao <jiewen....@intel.com>
Cc: Jordan Justen <jordan.l.jus...@intel.com>
Cc: Gerd Hoffmann <kra...@redhat.com>
Signed-off-by: Sunil V L <suni...@ventanamicro.com>
Acked-by: Ard Biesheuvel <a...@kernel.org>
Reviewed-by: Andrei Warkentin <andrei.warken...@intel.com>
Commit: f13264b340743bcd9ab62b6004b9fa0095000917
https://github.com/tianocore/edk2/commit/f13264b340743bcd9ab62b6004b9fa0095000917
Author: Sunil V L <suni...@ventanamicro.com>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
M ArmVirtPkg/ArmVirtCloudHv.dsc
M ArmVirtPkg/ArmVirtQemu.dsc
M ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc
M ArmVirtPkg/ArmVirtQemuKernel.dsc
M ArmVirtPkg/CloudHvPlatformHasAcpiDtDxe/CloudHvHasAcpiDtDxe.inf
M ArmVirtPkg/KvmtoolPlatformDxe/KvmtoolPlatformDxe.inf
Log Message:
-----------
ArmVirtPkg: Fix up the location of PlatformHasAcpiDtDxe
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
PlatformHasAcpiDtDxe is required by other architectures also.
Hence, it is moved to OvmfPkg. So, update the consumers of this
module with the new location.
Cc: Ard Biesheuvel <ardb+tianoc...@kernel.org>
Cc: Leif Lindholm <quic_llind...@quicinc.com>
Cc: Sami Mujawar <sami.muja...@arm.com>
Cc: Gerd Hoffmann <kra...@redhat.com>
Signed-off-by: Sunil V L <suni...@ventanamicro.com>
Reviewed-by: Andrei Warkentin <andrei.warken...@intel.com>
Acked-by: Ard Biesheuvel <a...@kernel.org>
Commit: d78df93863f9afe50f5900bec48482b1de5fa3de
https://github.com/tianocore/edk2/commit/d78df93863f9afe50f5900bec48482b1de5fa3de
Author: Sunil V L <suni...@ventanamicro.com>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
A OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/PlatformBm.c
A OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/PlatformBm.h
A
OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
A OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/QemuKernel.c
Log Message:
-----------
OvmfPkg/RiscVVirt: Add PlatformBootManagerLib library
RISC-V Qemu Virt platfform needs the PlatformBootManagerLib similar
to the one in ArmVirtPlatform. Add the library in OvmfPkg/RiscVVirt
leveraging the one from Arm.
Cc: Ard Biesheuvel <ardb+tianoc...@kernel.org>
Cc: Jiewen Yao <jiewen....@intel.com>
Cc: Jordan Justen <jordan.l.jus...@intel.com>
Cc: Gerd Hoffmann <kra...@redhat.com>
Signed-off-by: Sunil V L <suni...@ventanamicro.com>
Acked-by: Abner Chang <abner.ch...@amd.com>
Reviewed-by: Andrei Warkentin <andrei.warken...@intel.com>
Acked-by: Ard Biesheuvel <a...@kernel.org>
Acked-by: Jiewen Yao <jiewen....@intel.com>
Commit: 6720b8e46f9f72b97402c57083778bf15b6f6d5b
https://github.com/tianocore/edk2/commit/6720b8e46f9f72b97402c57083778bf15b6f6d5b
Author: Sunil V L <suni...@ventanamicro.com>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
A OvmfPkg/RiscVVirt/Library/PrePiHobListPointerLib/PrePiHobListPointer.c
A
OvmfPkg/RiscVVirt/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
Log Message:
-----------
OvmfPkg/RiscVVirt: Add PrePiHobListPointerLib library
Add the PrePiHobListPointerLib required for RISC-V Qemu Virt machine
since it follows PEIless design.
Cc: Ard Biesheuvel <ardb+tianoc...@kernel.org>
Cc: Jiewen Yao <jiewen....@intel.com>
Cc: Jordan Justen <jordan.l.jus...@intel.com>
Cc: Gerd Hoffmann <kra...@redhat.com>
Signed-off-by: Sunil V L <suni...@ventanamicro.com>
Acked-by: Abner Chang <abner.ch...@amd.com>
Reviewed-by: Andrei Warkentin <andrei.warken...@intel.com>
Acked-by: Jiewen Yao <jiewen....@intel.com>
Acked-by: Ard Biesheuvel <a...@kernel.org>
Commit: c126e3588d4081c59229247748e8fb7e3a65ba10
https://github.com/tianocore/edk2/commit/c126e3588d4081c59229247748e8fb7e3a65ba10
Author: Sunil V L <suni...@ventanamicro.com>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
A OvmfPkg/RiscVVirt/Library/ResetSystemLib/BaseResetSystemLib.inf
A OvmfPkg/RiscVVirt/Library/ResetSystemLib/ResetSystemLib.c
Log Message:
-----------
OvmfPkg/RiscVVirt: Add ResetSystemLib library
RISC-V Qemu virt uses SBI calls to implement the reset.
Add the base class library.
Cc: Ard Biesheuvel <ardb+tianoc...@kernel.org>
Cc: Jiewen Yao <jiewen....@intel.com>
Cc: Jordan Justen <jordan.l.jus...@intel.com>
Cc: Gerd Hoffmann <kra...@redhat.com>
Signed-off-by: Sunil V L <suni...@ventanamicro.com>
Acked-by: Abner Chang <abner.ch...@amd.com>
Reviewed-by: Andrei Warkentin <andrei.warken...@intel.com>
Acked-by: Ard Biesheuvel <a...@kernel.org>
Acked-by: Jiewen Yao <jiewen....@intel.com>
Commit: 6d5ae344cd1a4187334c6eeaa1c88aebe6881eff
https://github.com/tianocore/edk2/commit/6d5ae344cd1a4187334c6eeaa1c88aebe6881eff
Author: Sunil V L <suni...@ventanamicro.com>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
A OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c
A
OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.inf
Log Message:
-----------
OvmfPkg/RiscVVirt: Add VirtNorFlashPlatformLib library
Qemu NOR flash driver needs this library. Add this
library for RISC-V leveraged from SbsaQemu.
Cc: Ard Biesheuvel <ardb+tianoc...@kernel.org>
Cc: Jiewen Yao <jiewen....@intel.com>
Cc: Jordan Justen <jordan.l.jus...@intel.com>
Cc: Gerd Hoffmann <kra...@redhat.com>
Signed-off-by: Sunil V L <suni...@ventanamicro.com>
Acked-by: Abner Chang <abner.ch...@amd.com>
Reviewed-by: Andrei Warkentin <andrei.warken...@intel.com>
Acked-by: Jiewen Yao <jiewen....@intel.com>
Acked-by: Ard Biesheuvel <a...@kernel.org>
Commit: a43a62f9b0242aa87eeee7e8f0339ea00078fad2
https://github.com/tianocore/edk2/commit/a43a62f9b0242aa87eeee7e8f0339ea00078fad2
Author: Sunil V L <suni...@ventanamicro.com>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
A OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.c
A OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
Log Message:
-----------
OvmfPkg/RiscVVirt: Add PciCpuIo2Dxe module
Add PciCpuIo2Dxe driver to implement EFI_CPU_IO2_PROTOCOL
to add the translation for IO access. This is copied from
ArmPciCpuIo2Dxe driver.
Cc: Ard Biesheuvel <ardb+tianoc...@kernel.org>
Cc: Jiewen Yao <jiewen....@intel.com>
Cc: Jordan Justen <jordan.l.jus...@intel.com>
Cc: Gerd Hoffmann <kra...@redhat.com>
Signed-off-by: Sunil V L <suni...@ventanamicro.com>
Acked-by: Abner Chang <abner.ch...@amd.com>
Reviewed-by: Andrei Warkentin <andrei.warken...@intel.com>
Acked-by: Ard Biesheuvel <a...@kernel.org>
Acked-by: Jiewen Yao <jiewen....@intel.com>
Commit: e1aaef001fd2ddb8c7b9375056598773bde46414
https://github.com/tianocore/edk2/commit/e1aaef001fd2ddb8c7b9375056598773bde46414
Author: Sunil V L <suni...@ventanamicro.com>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
A OvmfPkg/RiscVVirt/Sec/Cpu.c
A OvmfPkg/RiscVVirt/Sec/Memory.c
A OvmfPkg/RiscVVirt/Sec/Platform.c
A OvmfPkg/RiscVVirt/Sec/SecEntry.S
A OvmfPkg/RiscVVirt/Sec/SecMain.c
A OvmfPkg/RiscVVirt/Sec/SecMain.h
A OvmfPkg/RiscVVirt/Sec/SecMain.inf
Log Message:
-----------
OvmfPkg/RiscVVirt: Add SEC module
Add the SEC module for RISC-V Qemu virt machine support.
It uses the PEI less design.
Cc: Ard Biesheuvel <ardb+tianoc...@kernel.org>
Cc: Jiewen Yao <jiewen....@intel.com>
Cc: Jordan Justen <jordan.l.jus...@intel.com>
Cc: Gerd Hoffmann <kra...@redhat.com>
Signed-off-by: Sunil V L <suni...@ventanamicro.com>
Acked-by: Abner Chang <abner.ch...@amd.com>
Reviewed-by: Andrei Warkentin <andrei.warken...@intel.com>
Acked-by: Jiewen Yao <jiewen....@intel.com>
Acked-by: Ard Biesheuvel <a...@kernel.org>
Commit: 92b27c2e6ada3b2d1521526f04967fb2aa555eb0
https://github.com/tianocore/edk2/commit/92b27c2e6ada3b2d1521526f04967fb2aa555eb0
Author: Sunil V L <suni...@ventanamicro.com>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
A OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
A OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc
A OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc
A OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
A OvmfPkg/RiscVVirt/VarStore.fdf.inc
Log Message:
-----------
OvmfPkg/RiscVVirt: Add build files for Qemu Virt platform
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
Add infrastructure files to build edk2 for RISC-V qemu virt machine.
- It follows PEI less design.
- EDK2 for qemu virt is booted in S-mode as a payload for M-mode FW
- Leveraged from ArmVirtQemu
Cc: Ard Biesheuvel <ardb+tianoc...@kernel.org>
Cc: Jiewen Yao <jiewen....@intel.com>
Cc: Jordan Justen <jordan.l.jus...@intel.com>
Cc: Gerd Hoffmann <kra...@redhat.com>
Signed-off-by: Sunil V L <suni...@ventanamicro.com>
Acked-by: Abner Chang <abner.ch...@amd.com>
Reviewed-by: Andrei Warkentin <andrei.warken...@intel.com>
Acked-by: Ard Biesheuvel <a...@kernel.org>
Acked-by: Jiewen Yao <jiewen....@intel.com>
Commit: 5c551d6d912967ada3084033acea8acf37256043
https://github.com/tianocore/edk2/commit/5c551d6d912967ada3084033acea8acf37256043
Author: Sunil V L <suni...@ventanamicro.com>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
M Maintainers.txt
Log Message:
-----------
Maintainers.txt: Add entry for OvmfPkg/RiscVVirt
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
RiscVVirt is created to support EDK2 for RISC-V qemu
virt machine platform. Add maintainer entries.
Cc: Andrew Fish <af...@apple.com>
Cc: Leif Lindholm <quic_llind...@quicinc.com>
Cc: Michael D Kinney <michael.d.kin...@intel.com>
Signed-off-by: Sunil V L <suni...@ventanamicro.com>
Reviewed-by: Andrei Warkentin <andrei.warken...@intel.com>
Reviewed-by: Jiewen Yao <jiewen....@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kin...@intel.com>
Acked-by: Ard Biesheuvel <a...@kernel.org>
Compare: https://github.com/tianocore/edk2/compare/38da9606f778...5c551d6d9129
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