Branch: refs/heads/master
Home: https://github.com/tianocore/edk2
Commit: da3dad181e17b8c3d5c7c1ee8f33ebabf0086d6f
https://github.com/tianocore/edk2/commit/da3dad181e17b8c3d5c7c1ee8f33ebabf0086d6f
Author: Dun Tan <dun....@intel.com>
Date: 2023-03-27 (Mon, 27 Mar 2023)
Changed paths:
M UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
Log Message:
-----------
UefiCpuPkg/CpuPageTableLib: Remove unneeded 'if' condition
Remove unneeded 'if' condition in CpuPageTableLib code.
The deleted code is in the code branch for present non-leaf parent
entry. So the 'if' check for (ParentPagingEntry->Pnle.Bits.Present
== 0) is always FALSE.
Signed-off-by: Dun Tan <dun....@intel.com>
Cc: Eric Dong <eric.d...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Tested-by: Gerd Hoffmann <kra...@redhat.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Commit: c18fbd2c3162e5aa0f8017cad5ec3dcc6ba9099b
https://github.com/tianocore/edk2/commit/c18fbd2c3162e5aa0f8017cad5ec3dcc6ba9099b
Author: Dun Tan <dun....@intel.com>
Date: 2023-03-27 (Mon, 27 Mar 2023)
Changed paths:
M UefiCpuPkg/Include/Library/CpuPageTableLib.h
M UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
Log Message:
-----------
UefiCpuPkg/CpuPageTableLib: Add check for input Length
Add check for input Length in PageTableMap (). Return
RETURN_SUCCESS when input Length is 0.
Signed-off-by: Dun Tan <dun....@intel.com>
Cc: Eric Dong <eric.d...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Tested-by: Gerd Hoffmann <kra...@redhat.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Commit: 563a2d2695891a709394ce39af8349a2dee64b4f
https://github.com/tianocore/edk2/commit/563a2d2695891a709394ce39af8349a2dee64b4f
Author: Dun Tan <dun....@intel.com>
Date: 2023-03-27 (Mon, 27 Mar 2023)
Changed paths:
M UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
Log Message:
-----------
UefiCpuPkg/CpuPageTableLib:Initialize some LocalVariable at beginning
Move some local variable initialization to the beginning of the
function. Also delete duplicated calculation for RegionLength.
Signed-off-by: Dun Tan <dun....@intel.com>
Cc: Eric Dong <eric.d...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Tested-by: Gerd Hoffmann <kra...@redhat.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Commit: 4904a2b1ecb700fce6085f3e0ae18a73aed97a2e
https://github.com/tianocore/edk2/commit/4904a2b1ecb700fce6085f3e0ae18a73aed97a2e
Author: Dun Tan <dun....@intel.com>
Date: 2023-03-27 (Mon, 27 Mar 2023)
Changed paths:
M UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
Log Message:
-----------
UefiCpuPkg/CpuPageTableLib: Fix the non-1:1 mapping issue
In previous code logic, when splitting a leaf parent entry to
smaller granularity child page table, if the parent entry
Attribute&Mask(without PageTableBaseAddress field) is equal to the
input attribute&mask(without PageTableBaseAddress field), the split
process won't happen. This may lead to failure in non-1:1 mapping.
For example, there is a page table in which [0, 1G] is mapped(Lv4[0]
,Lv3[0,0], a non-leaf level4 entry and a leaf level3 entry). And we
want to remap [0, 2M] linear address range to [1G, 1G + 2M] with the
same attibute. The expected behaviour should be: split Lv3[0,0]
entry into 512 level2 entries and remap the first level2 entry to
cover [0, 2M]. But the split won't happen in previous code since
PageTableBaseAddress of input Attribute is not checked.
So, when checking if a leaf parent entry needs to be splitted, we
should also check if PageTableBaseAddress calculated by parent entry
is equal to the value caculated by input attribute.
Signed-off-by: Dun Tan <dun....@intel.com>
Cc: Eric Dong <eric.d...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Tested-by: Gerd Hoffmann <kra...@redhat.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Commit: b6b54367c30f1f62a8b5228bc1dfb32246bc91be
https://github.com/tianocore/edk2/commit/b6b54367c30f1f62a8b5228bc1dfb32246bc91be
Author: Dun Tan <dun....@intel.com>
Date: 2023-03-27 (Mon, 27 Mar 2023)
Changed paths:
M UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
Log Message:
-----------
UefiCpuPkg/CpuPageTableLib:Clear PageSize bit(Bit7) for non-leaf
Clear PageSize bit(Bit7) for non-leaf entry in PageTableLibSetPnle.
This function is used to set non-leaf entry attributes so it should
make sure that the PageSize bit of the entry should be 0.
Signed-off-by: Dun Tan <dun....@intel.com>
Cc: Eric Dong <eric.d...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Tested-by: Gerd Hoffmann <kra...@redhat.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Commit: c90cb726f8755a7e9833e2802e35877cf1ecd3a9
https://github.com/tianocore/edk2/commit/c90cb726f8755a7e9833e2802e35877cf1ecd3a9
Author: Dun Tan <dun....@intel.com>
Date: 2023-03-27 (Mon, 27 Mar 2023)
Changed paths:
M UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
Log Message:
-----------
UefiCpuPkg/CpuPageTableLib: Fix issue when splitting leaf entry
When splitting leaf parent entry to smaller granularity, create
child page table before modifing parent entry. In previous code
logic, when splitting a leaf parent entry, parent entry will
point to a null 4k memory before child page table is created in
this 4k memory. When the page table to be modified is the page
table in CR3, if the executed CpuPageTableLib code is in the
range mapped by the modified leaf parent entry, then issue will
happen.
Signed-off-by: Dun Tan <dun....@intel.com>
Cc: Eric Dong <eric.d...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Tested-by: Gerd Hoffmann <kra...@redhat.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Commit: 96e8676577407e3270881a9e41b4ba257da986bc
https://github.com/tianocore/edk2/commit/96e8676577407e3270881a9e41b4ba257da986bc
Author: Dun Tan <dun....@intel.com>
Date: 2023-03-27 (Mon, 27 Mar 2023)
Changed paths:
M UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c
Log Message:
-----------
UefiCpuPkg/MpInitLib: Add code to initialize MapMask
In function CreatePageTable(), add code to initialize MapMask to
MAX_UINT64. When creating new page table or map non-present range
to present, all attributes should be provided.
Signed-off-by: Dun Tan <dun....@intel.com>
Cc: Eric Dong <eric.d...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Tested-by: Gerd Hoffmann <kra...@redhat.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Commit: a926c6c49e3966891b5e5e8fd2a0f5782660f3ac
https://github.com/tianocore/edk2/commit/a926c6c49e3966891b5e5e8fd2a0f5782660f3ac
Author: Dun Tan <dun....@intel.com>
Date: 2023-03-27 (Mon, 27 Mar 2023)
Changed paths:
M UefiCpuPkg/Include/Library/CpuPageTableLib.h
M UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
Log Message:
-----------
UefiCpuPkg/CpuPageTableLib:Add check for Mask and Attr
For different usage, check if the combination for Mask and
Attr is valid when creating or updating page table.
1.For non-present range
1.1Mask.Present is 0 but some other attributes is provided.
This case is invalid.
1.2Mask.Present is 1 and Attr.Present is 0. In this case,all
other attributes should not be provided.
1.3Mask.Present is 1 and Attr.Present is 1. In this case,all
attributes should be provided to intialize the attribute.
2.For present range
2.1Mask.Present is 1 and Attr.Present is 0.In this case, all
other attributes should not be provided.
All other usage for present range is permitted.
In the mentioned cases, 1.2 and 2.1 can be merged into 1 check.
Signed-off-by: Dun Tan <dun....@intel.com>
Cc: Eric Dong <eric.d...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Tested-by: Gerd Hoffmann <kra...@redhat.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Commit: 14ef21e5590eccfa35776f3518e8a7ef0a789a58
https://github.com/tianocore/edk2/commit/14ef21e5590eccfa35776f3518e8a7ef0a789a58
Author: Dun Tan <dun....@intel.com>
Date: 2023-03-27 (Mon, 27 Mar 2023)
Changed paths:
M UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c
Log Message:
-----------
UefiCpuPkg/CpuPageTableLib: Add manual test to check Mask and Attr
Add manual test case to check input Mask and Attribute. The check
steps are:
1.Create Page table to cover [0, 2G]. All fields of MapMask should
be set.
2.Update Page table to set [2G - 8K,2G] from present to non-present.
All fields of MapMask except present should not be set.
3.Still set [2G - 8K, 2G] as not present, this case is permitted.
But set [2G - 8K, 2G] as RW is not permitted.
4.Update Page table to set [2G - 8K, 2G] as present and RW. All
fields of MapMask should be set.
Signed-off-by: Dun Tan <dun....@intel.com>
Cc: Eric Dong <eric.d...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Tested-by: Gerd Hoffmann <kra...@redhat.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Commit: 661a669c8177d02cf89d03325fd4cb1392af2c99
https://github.com/tianocore/edk2/commit/661a669c8177d02cf89d03325fd4cb1392af2c99
Author: Dun Tan <dun....@intel.com>
Date: 2023-03-27 (Mon, 27 Mar 2023)
Changed paths:
M UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c
Log Message:
-----------
UefiCpuPkg/CpuPageTableLib:Modify RandomBoolean() in RandomTest
Add an input parameter to control the probability of returning
true. Change RandomBoolean() in RandomTest from 50% chance
returning true to returning true with the percentage of input
Probability.
Signed-off-by: Dun Tan <dun....@intel.com>
Cc: Eric Dong <eric.d...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Tested-by: Gerd Hoffmann <kra...@redhat.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Commit: ecfe6382c1f79a3bf0b9591eb3a34695fd3993e0
https://github.com/tianocore/edk2/commit/ecfe6382c1f79a3bf0b9591eb3a34695fd3993e0
Author: Dun Tan <dun....@intel.com>
Date: 2023-03-27 (Mon, 27 Mar 2023)
Changed paths:
M UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c
Log Message:
-----------
UefiCpuPkg/CpuPageTableLib: Add LastMapEntry pointer
Add LastMapEntry pointer to replace MapEntrys->Maps[MapsIndex]
in SingleMapEntryTest () of RandomTest.
Signed-off-by: Dun Tan <dun....@intel.com>
Cc: Eric Dong <eric.d...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Cc: Gerd Hoffmann <kra...@redhat.com>
Commit: cecf279c3234a405ae6bfe45194ca7c59eb10100
https://github.com/tianocore/edk2/commit/cecf279c3234a405ae6bfe45194ca7c59eb10100
Author: Dun Tan <dun....@intel.com>
Date: 2023-03-27 (Mon, 27 Mar 2023)
Changed paths:
M UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c
M UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c
Log Message:
-----------
UefiCpuPkg/CpuPageTableLib:Modify RandomTest to check Mask/Attr
Modify RandomTest to check invalid input. When creating new page
table or updating exsiting page table:
1.If set [LinearAddress, LinearAddress+Length] to non-present, all
other attributes should not be provided.
2.If [LinearAddress, LinearAddress+Length] contain non-present range,
the Returnstatus of PageTableMap() should be InvalidParameter when:
2.1Some of attributes are not provided when mapping non-present range
to present.
2.2Set any other attribute without setting the non-present range to
Present.
Signed-off-by: Dun Tan <dun....@intel.com>
Cc: Eric Dong <eric.d...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Tested-by: Gerd Hoffmann <kra...@redhat.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Cc: Zhiguang Liu <zhiguang....@intel.com>
Commit: 3b2661d247eb58bfad30662da434f73382d3e873
https://github.com/tianocore/edk2/commit/3b2661d247eb58bfad30662da434f73382d3e873
Author: Dun Tan <dun....@intel.com>
Date: 2023-03-27 (Mon, 27 Mar 2023)
Changed paths:
M UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c
Log Message:
-----------
UefiCpuPkg/CpuPageTableLib: Enable non-1:1 mapping in random test
Enable non-1:1 mapping in random test. In previous test, non-1:1
test will fail due to the non-1:1 mapping issue in CpuPageTableLib
and invalid Input Mask when creating new page table or mapping
not-present range. Now these issue have been fixed.
Signed-off-by: Dun Tan <dun....@intel.com>
Cc: Eric Dong <eric.d...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Tested-by: Gerd Hoffmann <kra...@redhat.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Commit: c8c6cf149d07e2749ce7a17c084ab658af2e9cdd
https://github.com/tianocore/edk2/commit/c8c6cf149d07e2749ce7a17c084ab658af2e9cdd
Author: Dun Tan <dun....@intel.com>
Date: 2023-03-27 (Mon, 27 Mar 2023)
Changed paths:
M UefiCpuPkg/Include/Library/CpuPageTableLib.h
M UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
M UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c
M UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c
M UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c
Log Message:
-----------
UefiCpuPkg/CpuPageTableLib: Add OUTPUT IsModified parameter.
Add OUTPUT IsModified parameter in PageTableMap() to indicate
if page table has been modified. With this parameter, caller
can know if need to call FlushTlb when the page table is in CR3.
Signed-off-by: Dun Tan <dun....@intel.com>
Cc: Eric Dong <eric.d...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Tested-by: Gerd Hoffmann <kra...@redhat.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Commit: 8727cc9a8e96608abfc29f5367a1929aae685f95
https://github.com/tianocore/edk2/commit/8727cc9a8e96608abfc29f5367a1929aae685f95
Author: Dun Tan <dun....@intel.com>
Date: 2023-03-27 (Mon, 27 Mar 2023)
Changed paths:
M UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c
Log Message:
-----------
UefiCpuPkg/CpuPageTableLib: Modify RandomTest to check IsModified
Modify RandomTest to check if parameter IsModified of
PageTableMap() correctlly indicates whether input page table
is modified or not.
Signed-off-by: Dun Tan <dun....@intel.com>
Cc: Eric Dong <eric.d...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Tested-by: Gerd Hoffmann <kra...@redhat.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Cc: Zhiguang Liu <zhiguang....@intel.com>
Commit: 2e01a5c1288590ce6306717a5413bd789f495c12
https://github.com/tianocore/edk2/commit/2e01a5c1288590ce6306717a5413bd789f495c12
Author: Zhiguang Liu <zhiguang....@intel.com>
Date: 2023-03-27 (Mon, 27 Mar 2023)
Changed paths:
M UefiCpuPkg/Include/Library/CpuPageTableLib.h
M UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h
M UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
Log Message:
-----------
UefiCpuPkg: Fix IA32 build failure in CpuPageTableLib.inf
The definition of IA32_MAP_ATTRIBUTE has 64 bits, and one of the bit
field PageTableBaseAddress is from bit 12 to bit 52. This means if the
compiler treats the 64bits value as two UINT32 value, the field
PageTableBaseAddress spans two UINT32 value. That's why when building in
NOOPT mode in IA32, the below issue is noticed:
unresolved external symbol __allshl
This patch fix the build failure by seperate field PageTableBaseAddress
into two fields, make sure no field spans two UINT32 value.
Cc: Eric Dong <eric.d...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Tested-by: Gerd Hoffmann <kra...@redhat.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Signed-off-by: Zhiguang Liu <zhiguang....@intel.com>
Signed-off-by: Ray Ni <ray...@intel.com>
Commit: aa3153b872e704605d710edf454a4f301632a4e5
https://github.com/tianocore/edk2/commit/aa3153b872e704605d710edf454a4f301632a4e5
Author: Zhiguang Liu <zhiguang....@intel.com>
Date: 2023-03-27 (Mon, 27 Mar 2023)
Changed paths:
M UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c
M UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c
M UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c
Log Message:
-----------
UefiCpuPkg: Modify UnitTest code since tested API is changed
Last commit changed the CpuPageTableLib API PageTableMap, unit
test code should also be modified.
Cc: Eric Dong <eric.d...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Tested-by: Gerd Hoffmann <kra...@redhat.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Signed-off-by: Zhiguang Liu <zhiguang....@intel.com>
Commit: f7686f2727ae854fcf6c9518d8a782817a15bb43
https://github.com/tianocore/edk2/commit/f7686f2727ae854fcf6c9518d8a782817a15bb43
Author: Dun Tan <dun....@intel.com>
Date: 2023-03-27 (Mon, 27 Mar 2023)
Changed paths:
M UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
Log Message:
-----------
UefiCpuPkg/CpuPageTableLib: Add check for page table creation
Add code to compare ParentPagingEntry Attribute&Mask and input
Attribute&Mask to decide if new next level page table is needed
in non-present ParentPagingEntry condition. This can help avoid
unneccessary page table creation.
For example, there is a page table in which [0, 1G] is mapped(Lv4[0]
,Lv3[0,0], a non-leaf level4 entry and a leaf level3 entry).And we
only want to map [1G, 1G+2M] linear address still as non-present.
The expected behaviour should be nothing happens in the process.
However, previous code logic doesn't check if ParentPagingEntry
Attribute&Mask and input Attribute&Mask are the same in non-present
ParentPagingEntry condition. Then a new 4K memory is allocated for
Lv2 since 1G+2M is not 1G-aligned.
So when ParentPagingEntry is non-present, before allocate 4K memory
for next level paging, we also check if ParentPagingEntry Attribute&
Mask and input Attribute&Mask are the same.
Signed-off-by: Dun Tan <dun....@intel.com>
Cc: Eric Dong <eric.d...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Tested-by: Gerd Hoffmann <kra...@redhat.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Commit: 878cbd871df598cf9ec578ec08ac9ea4c5255f69
https://github.com/tianocore/edk2/commit/878cbd871df598cf9ec578ec08ac9ea4c5255f69
Author: Dun Tan <dun....@intel.com>
Date: 2023-03-27 (Mon, 27 Mar 2023)
Changed paths:
M UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
Log Message:
-----------
UefiCpuPkg: Combine branch for non-present and leaf ParentEntry
Combine 'if' condition branch for non-present and leaf Parent
Entry in PageTableLibMapInLevel. Most steps of these two condition
are the same. This commit doesn't change any functionality.
Signed-off-by: Dun Tan <dun....@intel.com>
Cc: Eric Dong <eric.d...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Tested-by: Gerd Hoffmann <kra...@redhat.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Commit: aad9a301442a81c44333b44e01e39a10174930c1
https://github.com/tianocore/edk2/commit/aad9a301442a81c44333b44e01e39a10174930c1
Author: Dun Tan <dun....@intel.com>
Date: 2023-03-27 (Mon, 27 Mar 2023)
Changed paths:
M UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h
M UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
M UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableParse.c
Log Message:
-----------
UefiCpuPkg/CpuPageTableLib: Enable PAE paging
Modify CpuPageTableLib code to enable PAE paging.
In PageTableMap() API:
When creating new PAE page table, after creating page table,
set all MustBeZero fields of 4 PDPTE to 0. The MustBeZero
fields are treated as RW and other attributes by the common
map logic. So they might be set to 1.
When updating exsiting PAE page table, the special steps are:
1.Prepare 4K-aligned 32bytes memory in stack for 4 temp PDPTE.
2.Copy original 4 PDPTE to the 4 temp PDPTE and set the RW,
UserSupervisor to 1 and set Nx of 4 temp PDPTE to 0.
4.After updating the page table, set the MustBeZero fields of
4 temp PDPTE to 0.
5.Copy the temp PDPTE to original PDPTE.
In PageTableParse() API, also create 4 temp PDPTE in stack.
Copy original 4 PDPTE to the 4 temp PDPTE. Then set the RW,
UserSupervisor to 1 and set Nx of 4 temp PDPTE to 0. Finally
use the address of temp PDPTE as the page table address.
Signed-off-by: Dun Tan <dun....@intel.com>
Cc: Eric Dong <eric.d...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Tested-by: Gerd Hoffmann <kra...@redhat.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Commit: aea5930c40326f2c7981fd42239faeec32ef3e71
https://github.com/tianocore/edk2/commit/aea5930c40326f2c7981fd42239faeec32ef3e71
Author: Dun Tan <dun....@intel.com>
Date: 2023-03-27 (Mon, 27 Mar 2023)
Changed paths:
M UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c
M UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c
M UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c
Log Message:
-----------
UefiCpuPkg/CpuPageTableLib: Add RandomTest for PAE paging
Add RandomTest for PAE paging.
Signed-off-by: Dun Tan <dun....@intel.com>
Cc: Eric Dong <eric.d...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Tested-by: Gerd Hoffmann <kra...@redhat.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Commit: 2bc854588309b6a9b348655297f3f82165de23a7
https://github.com/tianocore/edk2/commit/2bc854588309b6a9b348655297f3f82165de23a7
Author: Dun Tan <dun....@intel.com>
Date: 2023-03-27 (Mon, 27 Mar 2023)
Changed paths:
M UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c
Log Message:
-----------
UefiCpuPkg/CpuPageTableLib: Reduce the number of random tests
Reduce the number of random tests. In previous patch, non-1:1
mapping is enbaled and it may need more than an hour and a half
for the CI test, which may lead to CI timeout. Reduce the number
of random test count to pass the CI.
Signed-off-by: Dun Tan <dun....@intel.com>
Cc: Eric Dong <eric.d...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Tested-by: Gerd Hoffmann <kra...@redhat.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Compare: https://github.com/tianocore/edk2/compare/d55d73152ebf...2bc854588309
_______________________________________________
edk2-commits mailing list
edk2-commits@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/edk2-commits
