Branch: refs/heads/master
Home: https://github.com/tianocore/edk2
Commit: 2900e755113c8f923e16a8b5f16258afd25221a0
https://github.com/tianocore/edk2/commit/2900e755113c8f923e16a8b5f16258afd25221a0
Author: Andrei Warkentin <andrei.warken...@intel.com>
Date: 2023-05-17 (Wed, 17 May 2023)
Changed paths:
M MdePkg/Include/Library/BaseRiscVSbiLib.h
M MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.c
Log Message:
-----------
MdePkg: BaseRiscVSbiLib: make more useful to consumers
Add a few more definitions and make SbiCall and TranslateError
usable (not static) by library users.
Cc: Daniel Schaefer <g...@danielschaefer.me>
Signed-off-by: Andrei Warkentin <andrei.warken...@intel.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Reviewed-by: Sunil V L <suni...@ventanamicro.com>
Reviewed-by: Michael D Kinney <michael.d.kin...@intel.com>
Commit: 45da4e313579f0bcea42062c675c8333d3bad050
https://github.com/tianocore/edk2/commit/45da4e313579f0bcea42062c675c8333d3bad050
Author: Andrei Warkentin <andrei.warken...@intel.com>
Date: 2023-05-17 (Wed, 17 May 2023)
Changed paths:
A MdePkg/Library/BaseSerialPortLibRiscVSbiLib/BaseSerialPortLibRiscVSbiLib.c
A
MdePkg/Library/BaseSerialPortLibRiscVSbiLib/BaseSerialPortLibRiscVSbiLib.inf
A
MdePkg/Library/BaseSerialPortLibRiscVSbiLib/BaseSerialPortLibRiscVSbiLib.uni
A
MdePkg/Library/BaseSerialPortLibRiscVSbiLib/BaseSerialPortLibRiscVSbiLibRam.c
A
MdePkg/Library/BaseSerialPortLibRiscVSbiLib/BaseSerialPortLibRiscVSbiLibRam.inf
A MdePkg/Library/BaseSerialPortLibRiscVSbiLib/Common.c
A MdePkg/Library/BaseSerialPortLibRiscVSbiLib/Common.h
M MdePkg/MdePkg.dsc
Log Message:
-----------
MdePkg: add SBI-based SerialPortLib for RISC-V
These are implementations of SerialPortLib using SBI console services.
- BaseSerialPortLibRiscVSbiLib is appropriate for SEC/PEI (XIP)
environments
- BaseSerialPortLibRiscVSbiLibRam is appropriate for PrePI/DXE
environments
Tested with:
- Qemu RiscVVirt (non-DBCN case, backed by UART)
- TinyEMU + RiscVVirt (non-DBCN case, HTIF)
- TinyEMU + RiscVVirt (DBCN case, HTIF)
Cc: Daniel Schaefer <g...@danielschaefer.me>
Cc: Sunil V L <suni...@ventanamicro.com>
Cc: Michael D Kinney <michael.d.kin...@intel.com>
Cc: Liming Gao <gaolim...@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang....@intel.com>
Signed-off-by: Andrei Warkentin <andrei.warken...@intel.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Reviewed-by: Michael D Kinney <michael.d.kin...@intel.com>
Commit: 0abfb0be6cf78a8e962383e85cec57851ddae5bc
https://github.com/tianocore/edk2/commit/0abfb0be6cf78a8e962383e85cec57851ddae5bc
Author: Andrei Warkentin <andrei.warken...@intel.com>
Date: 2023-05-17 (Wed, 17 May 2023)
Changed paths:
M OvmfPkg/RiscVVirt/Sec/SecMain.c
M OvmfPkg/RiscVVirt/Sec/SecMain.h
M OvmfPkg/RiscVVirt/Sec/SecMain.inf
Log Message:
-----------
OvmfPkg: RiscVVirt: Add missing SerialPortInitialize to Sec
If the SerialPortLib had any initialization needed, this
would be skipped in the RiscVVirt Sec. Follow the example
seen elsewhere (ArmVirtPkg PrePi).
Seen with BaseSerialPortLibRiscVSbiLibRam not using DBCN in Sec,
yet using DBCN elsewhere.
Cc: Daniel Schaefer <g...@danielschaefer.me>
Signed-off-by: Andrei Warkentin <andrei.warken...@intel.com>
Reviewed-by: Sunil V L <suni...@ventanamicro.com>
Reviewed-by: Michael D Kinney <michael.d.kin...@intel.com>
Compare: https://github.com/tianocore/edk2/compare/cafb4f3f36e2...0abfb0be6cf7
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