Branch: refs/heads/master
Home: https://github.com/tianocore/edk2
Commit: 5ce29ae84db340244c3c3299f84713a88dec5171
https://github.com/tianocore/edk2/commit/5ce29ae84db340244c3c3299f84713a88dec5171
Author: Ard Biesheuvel <a...@kernel.org>
Date: 2023-05-23 (Tue, 23 May 2023)
Changed paths:
M ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S
Log Message:
-----------
ArmPkg/ArmMmuLib AARCH64: Add missing ISB after page table update
The helper that updates live page table entries writes a zero entry,
invalidates the covered address range from the TLBs, and finally writes
the actual entry. This ensures that no TLB conflicts can occur.
Writing the final entry needs to complete before any translations can be
performed, as otherwise, the zero entry, which describes an invalid
translation, may be observed by the page table walker, resulting in a
translation fault. For this reason, the final write is followed by a DSB
barrier instruction.
However, this barrier will not stall the pipeline, and instruction
fetches may still hit this invalid translation, as has been observed and
reported by Oliver. To ensure that the new translation is fully active
before returning from this helper, we have to insert an ISB barrier as
well.
Reported-by: Oliver Steffen <ostef...@redhat.com>
Tested-by: Oliver Steffen <ostef...@redhat.com>
Reviewed-by: Leif Lindholm <quic_llind...@quicinc.com>
Acked-by: Michael D Kinney <michael.d.kin...@intel.com>
Signed-off-by: Ard Biesheuvel <a...@kernel.org>
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