Branch: refs/heads/master
Home: https://github.com/tianocore/edk2
Commit: cc62b85a4ac61c553a3ff1a1e68b8fe3d8515476
https://github.com/tianocore/edk2/commit/cc62b85a4ac61c553a3ff1a1e68b8fe3d8515476
Author: Liu, Zhiguang <zhiguang....@intel.com>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm
M UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm
Log Message:
-----------
UefiCpuPkg/ResetVector: Rename macros about page table.
This patch only renames macro, with no code logic impacted.
Two purpose to rename macro:
1. Align some macro name in PageTables1G.asm and PageTables2M.asm, so
that these two files can be easily combined later.
2. Some Macro names such as PDP are not accurate, since 4 level page
entry also uses this macro. PAGE_NLE (no leaf entry) is better
Cc: Eric Dong <eric.d...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Tested-by: Gerd Hoffmann <kra...@redhat.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Cc: Debkumar De <debkumar...@intel.com>
Cc: Catharine West <catharine.w...@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang....@intel.com>
Commit: c19e3f578f51f9ce6645a319c83b7476c081fcbb
https://github.com/tianocore/edk2/commit/c19e3f578f51f9ce6645a319c83b7476c081fcbb
Author: Liu, Zhiguang <zhiguang....@intel.com>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
M UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm
M UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm
Log Message:
-----------
UefiCpuPkg/ResetVector: Simplify page table creation in ResetVector
Currently, page table creation has many hard-code values about the
offset to the start of page table. To simplify it, add Labels such
as Pml4, Pdp and Pd, so that we can remove many hard-code values
Cc: Eric Dong <eric.d...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Tested-by: Gerd Hoffmann <kra...@redhat.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Cc: Debkumar De <debkumar...@intel.com>
Cc: Catharine West <catharine.w...@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang....@intel.com>
Commit: 0fba57da65ea12eda18203cda52766888cbe95fe
https://github.com/tianocore/edk2/commit/0fba57da65ea12eda18203cda52766888cbe95fe
Author: Liu, Zhiguang <zhiguang....@intel.com>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
A UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm
R UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm
R UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm
Log Message:
-----------
UefiCpuPkg/ResetVector: Combine PageTables1G.asm and PageTables2M.asm
Combine PageTables1G.asm and PageTables2M.asm to reuse code.
Cc: Eric Dong <eric.d...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Tested-by: Gerd Hoffmann <kra...@redhat.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Cc: Debkumar De <debkumar...@intel.com>
Cc: Catharine West <catharine.w...@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang....@intel.com>
Commit: d064a6f7901c46e23fc60c0d9b4bf5497893146e
https://github.com/tianocore/edk2/commit/d064a6f7901c46e23fc60c0d9b4bf5497893146e
Author: Liu, Zhiguang <zhiguang....@intel.com>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm
Log Message:
-----------
UefiCpuPkg/ResetVector: Modify Page Table in ResetVector
In ResetVector, if create page table, its highest address is fixed
because after page table, code layout is fixed(4K for normal code,
and another 4K only contains reset vector code).
Today's implementation organizes the page table as following if 1G
page table is used:
4G-16K: PML4 page (PML4[0] points to 4G-12K)
4G-12K: PDP page
CR3 is set to 4G-16K
When 2M page table is used, the layout is as following:
4G-32K: PML4 page (PML4[0] points to 4G-28K)
4G-28K: PDP page (PDP entries point to PD pages)
4G-24K: PD page mapping 0-1G
4G-20K: PD page mapping 1-2G
4G-16K: PD page mapping 2-3G
4G-12K: PD page mapping 3-4G
CR3 is set to 4G-32K
CR3 doesn't point to a fixed location which is a bit hard to debug at
runtime.
The new page table layout will always put PML4 in highest address
When 1G page table is used, the layout is as following:
4G-16K: PDP page
4G-12K: PML4 page (PML4[0] points to 4G-16K)
When 2M page table is used, the layout is as following:
4G-32K: PD page mapping 0-1G
4G-28K: PD page mapping 1-2G
4G-24K: PD page mapping 2-3G
4G-20K: PD page mapping 3-4G
4G-16K: PDP page (PDP entries point to PD pages)
4G-12K: PML4 page (PML4[0] points to 4G-16K)
CR3 is always set to 4G-12K
So, this patch can improve debuggability by make sure the init
CR3 pointing to a fixed address(4G-12K).
Cc: Eric Dong <eric.d...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Tested-by: Gerd Hoffmann <kra...@redhat.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Cc: Debkumar De <debkumar...@intel.com>
Cc: Catharine West <catharine.w...@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang....@intel.com>
Commit: 0f9283429dd487deeeb264ee5670551d596fc208
https://github.com/tianocore/edk2/commit/0f9283429dd487deeeb264ee5670551d596fc208
Author: Zhiguang Liu <zhiguang....@intel.com>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
M UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm
Log Message:
-----------
UefiCpuPkg/ResetVector: Support 5 level page table in ResetVector
Add a macro USE_5_LEVEL_PAGE_TABLE to determine whether to create
5 level page table.
If macro USE_5_LEVEL_PAGE_TABLE is defined, PML5Table is created
at (4G-12K), while PML4Table is at (4G-16K). In runtime check, if
5level paging is supported, use PML5Table, otherwise, use PML4Table.
If macro USE_5_LEVEL_PAGE_TABLE is not defined, to save space, 5level
paging is not created, and 4level paging is at (4G-12K) and be used.
Cc: Eric Dong <eric.d...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Cc: Gerd Hoffmann <kra...@redhat.com>
Cc: Debkumar De <debkumar...@intel.com>
Cc: Catharine West <catharine.w...@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang....@intel.com>
Compare: https://github.com/tianocore/edk2/compare/48c53994e649...0f9283429dd4
_______________________________________________
edk2-commits mailing list
edk2-commits@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/edk2-commits
