Branch: refs/heads/master
Home: https://github.com/tianocore/edk2
Commit: b4d3b7797347c37b68bd9b9b6de0e75d9f447b14
https://github.com/tianocore/edk2/commit/b4d3b7797347c37b68bd9b9b6de0e75d9f447b14
Author: Jiaxin Wu <jiaxin...@intel.com>
Date: 2023-05-31 (Wed, 31 May 2023)
Changed paths:
M UefiCpuPkg/SecCore/SecCore.inf
M UefiCpuPkg/SecCore/SecCoreNative.inf
M UefiCpuPkg/SecCore/SecMain.c
M UefiCpuPkg/SecCore/SecMain.h
Log Message:
-----------
UefiCpuPkg/SecCore: Migrate page table to permanent memory
Background:
For arch X64, system will enable the page table in SPI to cover 0-512G
range via CR4.PAE & MSR.LME & CR0.PG & CR3 setting (see ResetVector code).
Existing code doesn't cover the higher address access above 512G before
memory-discovered callback. That will be potential problem if system
access the higher address after the transition from temporary RAM to
permanent MEM RAM.
Solution:
This patch is to migrate page table to permanent memory to map entire physical
address space if CR0.PG is set during temporary RAM Done.
Cc: Eric Dong <eric.d...@intel.com>
Cc: Ray Ni <ray...@intel.com>
Cc: Zeng Star <star.z...@intel.com>
Cc: Gerd Hoffmann <kra...@redhat.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Signed-off-by: Jiaxin Wu <jiaxin...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Commit: 56ad09ba75bef5f095a1a48e365d65195ba45d10
https://github.com/tianocore/edk2/commit/56ad09ba75bef5f095a1a48e365d65195ba45d10
Author: Jiaxin Wu <jiaxin...@intel.com>
Date: 2023-05-31 (Wed, 31 May 2023)
Changed paths:
M UefiCpuPkg/CpuMpPei/CpuMpPei.h
M UefiCpuPkg/CpuMpPei/CpuMpPei.inf
M UefiCpuPkg/CpuMpPei/CpuPaging.c
Log Message:
-----------
UefiCpuPkg/CpuMpPei: Conditionally enable PAE paging in 32bit mode
Some security features depend on the page table enabling. So, This
patch is to enable paging if it is not enabled (32bit mode)"
Cc: Eric Dong <eric.d...@intel.com>
Cc: Ray Ni <ray...@intel.com>
Cc: Zeng Star <star.z...@intel.com>
Cc: Gerd Hoffmann <kra...@redhat.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Signed-off-by: Jiaxin Wu <jiaxin...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Commit: 0d382976c29036f3397b1e5cf6dca87fc97949bb
https://github.com/tianocore/edk2/commit/0d382976c29036f3397b1e5cf6dca87fc97949bb
Author: Jiaxin Wu <jiaxin...@intel.com>
Date: 2023-05-31 (Wed, 31 May 2023)
Changed paths:
M MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
Log Message:
-----------
MdeModulePkg/DxeIpl: Align Page table Level setting with previous level.
System paging 5 level enabled or not can be checked via CR4.LA57, system
preferred Page table Level (PcdUse5LevelPageTable) must align with previous
level for 64bit long mode.
This patch is to do the wise check:
If cpu has already run in 64bit long mode PEI, Page table Level in DXE
must align with previous level.
If cpu runs in 32bit protected mode PEI, Page table Level in DXE is decided
by PCD and feature capability.
Cc: Dandan Bi <dandan...@intel.com>
Cc: Liming Gao <gaolim...@byosoft.com.cn>
Cc: Eric Dong <eric.d...@intel.com>
Cc: Ray Ni <ray...@intel.com>
Cc: Zeng Star <star.z...@intel.com>
Cc: Gerd Hoffmann <kra...@redhat.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Signed-off-by: Jiaxin Wu <jiaxin...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Commit: 55bee4a9dee82722ed9e1d5c1021d500c2c131e5
https://github.com/tianocore/edk2/commit/55bee4a9dee82722ed9e1d5c1021d500c2c131e5
Author: Jiaxin Wu <jiaxin...@intel.com>
Date: 2023-05-31 (Wed, 31 May 2023)
Changed paths:
M OvmfPkg/AmdSev/AmdSevX64.dsc
M OvmfPkg/CloudHv/CloudHvX64.dsc
M OvmfPkg/IntelTdx/IntelTdxX64.dsc
M OvmfPkg/Microvm/MicrovmX64.dsc
M OvmfPkg/OvmfPkgIa32.dsc
M OvmfPkg/OvmfPkgIa32X64.dsc
M OvmfPkg/OvmfPkgX64.dsc
M OvmfPkg/OvmfXen.dsc
Log Message:
-----------
OvmfPkg: Add CpuPageTableLib required by SecCore & CpuMpPei
Add CpuPageTableLib required by SecCore & CpuMpPei in OvmfPkg.
Cc: Ard Biesheuvel <ardb+tianoc...@kernel.org>
Cc: Jiewen Yao <jiewen....@intel.com>
Cc: Jordan Justen <jordan.l.jus...@intel.com>
Cc: Gerd Hoffmann <kra...@redhat.com>
Cc: Ray Ni <ray...@intel.com>
Cc: Zeng Star <star.z...@intel.com>
Signed-off-by: Jiaxin Wu <jiaxin...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Commit: d8e5d35ede7158ccbb9abf600e65b9aa6e043f74
https://github.com/tianocore/edk2/commit/d8e5d35ede7158ccbb9abf600e65b9aa6e043f74
Author: Jiaxin Wu <jiaxin...@intel.com>
Date: 2023-05-31 (Wed, 31 May 2023)
Changed paths:
M UefiPayloadPkg/UefiPayloadPkg.dsc
Log Message:
-----------
UefiPayloadPkg: Add CpuPageTableLib required by SecCore & CpuMpPei
Add CpuPageTableLib required by SecCore & CpuMpPei in UefiPayloadPkg.
Cc: Guo Dong <guo.d...@intel.com>
Cc: Sean Rhodes <sean@starlabs.systems>
Cc: James Lu <james...@intel.com>
Cc: Gua Guo <gua....@intel.com>
Cc: Ray Ni <ray...@intel.com>
Cc: Zeng Star <star.z...@intel.com>
Signed-off-by: Jiaxin Wu <jiaxin...@intel.com>
Reviewed-by: Ray Ni <ray...@intel.com>
Reviewed-by: Gua Guo <gua....@intel.com>
Compare: https://github.com/tianocore/edk2/compare/0f9283429dd4...d8e5d35ede71
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