Branch: refs/heads/master
Home: https://github.com/tianocore/edk2
Commit: 30a25f277821a1c8a168f6f3050721aa13f44b8d
https://github.com/tianocore/edk2/commit/30a25f277821a1c8a168f6f3050721aa13f44b8d
Author: Zhou Jianfeng <[email protected]>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
Log Message:
-----------
UefiCpuPkg: Reduce and optimize access to attribute
This commit is to reduce and optimize access to
attribute in CpuPageTableLib.
Unreasonable writing to attribute of page table may
leads to expection.
The assembly code for C code Pnle->Bits.Present =
Attribute->Bits.Present looks like:
and dword [rcx], 0xfffffffe
and eax, 0x1
or [rcx], eax
In case Pnle->Bits.Present and Attribute->Bits.Present
is 1, Pnle->Bits.Present will be set to 0 for short
time(2 instructions) which is unexpected. If some other
core is accessing the page, it may leads to expection.
This change reduce and optimize access to attribute of
page table, attribute of page table is set only when it
need to be changed.
Signed-off-by: Zhou Jianfeng <[email protected]>
Reviewed-by: Ray Ni <[email protected]>
Reviewed-by: Jiaxin Wu <[email protected]>
Cc: Laszlo Ersek <[email protected]>
Cc: Rahul Kumar <[email protected]>
Cc: Gerd Hoffmann <[email protected]>
Commit: 397a084b9ba159050825447db2b6a1177195d0be
https://github.com/tianocore/edk2/commit/397a084b9ba159050825447db2b6a1177195d0be
Author: Dun Tan <[email protected]>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M UefiCpuPkg/Include/Library/CpuPageTableLib.h
Log Message:
-----------
UefiCpuPkg: Add more Paging mode enumeration
Add more Paging mode enumeration in CpuPageTableLib
to support forced mapping a range in 4K page
granularity.
Signed-off-by: Dun Tan <[email protected]>
Reviewed-by: Ray Ni <[email protected]>
Reviewed-by: Jiaxin Wu <[email protected]>
Cc: Laszlo Ersek <[email protected]>
Cc: Rahul Kumar <[email protected]>
Cc: Gerd Hoffmann <[email protected]>
Commit: ae59b8ba4166384cbfa32a921aac289bcff2aef9
https://github.com/tianocore/edk2/commit/ae59b8ba4166384cbfa32a921aac289bcff2aef9
Author: Dun Tan <[email protected]>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
Log Message:
-----------
UefiCpuPkg/PiSmmCpuDxeSmm:Map SMRAM in 4K page granularity
This patch is to map SMRAM in 4K page granularity
during SMM page table initialization(SmmInitPageTable)
so as to avoid the SMRAM paging-structure layout
change when SMI happens (PerformRemainingTasks).
The reason is to avoid the Paging-Structure change
impact to the multiple Processors. Refer SDM section
"4.10.4" & "4.10.5".
Currently, SMM BSP needs to update the SMRAM range
paging attribute in smm page table according to the
SmmMemoryAttributesTable when SMM ready to lock
happens. If the SMRAM range is not 4k mapped in page
table, the page table update process may split 1G/2M
paging entries to 4k ones.Meanwhile, all APs are still
running in SMI, which might access the affected
linear-address range between the time of modification
and the time of invalidation access. That will be
a potential problem leading exception happens.
Signed-off-by: Dun Tan <[email protected]>
Reviewed-by: Ray Ni <[email protected]>
Reviewed-by: Jiaxin Wu <[email protected]>
Cc: Laszlo Ersek <[email protected]>
Cc: Rahul Kumar <[email protected]>
Cc: Gerd Hoffmann <[email protected]>
Compare: https://github.com/tianocore/edk2/compare/056b4bf74bf5...ae59b8ba4166
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