Branch: refs/heads/master
Home: https://github.com/tianocore/edk2
Commit: 1c0d4ae2c0fd24164873947c2e262c499ecf13b5
https://github.com/tianocore/edk2/commit/1c0d4ae2c0fd24164873947c2e262c499ecf13b5
Author: Xianglei Cai <[email protected]>
Date: 2024-05-07 (Tue, 07 May 2024)
Changed paths:
M MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h
M MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
M MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
M MdeModulePkg/MdeModulePkg.dec
Log Message:
-----------
MdeModulePkg/XhciDxe: Add PCD for the delay of HCRST
https://bugzilla.tianocore.org/show_bug.cgi?id=4727
Recently some of XHCI host controllers require to have
extra 1ms delay before accessing any MMIO register
during reset. PHY transition from P3 to P0 can take
around 1.3ms and the xHCI reset can take around 1.5ms.
Add PCD to control the delay, the default is 2 ms.
Cc: Ray Ni <[email protected]>
Cc: Liming Gao <[email protected]>
Cc: Krzysztof Lewandowski <[email protected]>
Cc: Jenny Huang <[email protected]>
Cc: More Shih <[email protected]>
Cc: Ian Chiu <[email protected]>
Signed-off-by: Xianglei Cai <[email protected]>
Reviewed-by: Krzysztof Lewandowski <[email protected]>
Reviewed-by: Liming Gao <[email protected]>
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