Branch: refs/heads/master
Home: https://github.com/tianocore/edk2
Commit: b54bc983c6102a59c9e0472dd0406ac9ccbaa0bf
https://github.com/tianocore/edk2/commit/b54bc983c6102a59c9e0472dd0406ac9ccbaa0bf
Author: Dhaval <dha...@rivosinc.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M MdePkg/Include/Register/RiscV64/RiscVEncoding.h
M MdePkg/Library/BaseRngLib/BaseRngLib.inf
A MdePkg/Library/BaseRngLib/Riscv/Rng.c
A MdePkg/Library/BaseRngLib/Riscv/Seed.S
M MdePkg/MdePkg.dec
Log Message:
-----------
MdePkg/Library: Add RISCV64 support to BaseRngLib
The ratified RISC-V crypto scalar extensions provide entropy bits via the
seed CSR, as exposed by the Zkr extension. The Zkr extension is ratified
and provides 16 bits of entropy seed when reading the SEED CSR.
Guarded by a RISCV64 Feature PCD, 64-bit random numbers can be
accumulated from the `seed` CSR. This driver is based on the driver in
the Linux kernel.
Cc: Liming Gao <gaolim...@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kin...@intel.com>
Cc: Zhiguang Liu <zhiguang....@intel.com>
Signed-off-by: Dhaval Sharma <dha...@rivosinc.com>
Co-authored-by: Tim Wawrzynczak <t...@rivosinc.com>
Commit: 91226e1eecacac832e5091d6a1867dc52666ee85
https://github.com/tianocore/edk2/commit/91226e1eecacac832e5091d6a1867dc52666ee85
Author: Dhaval <dha...@rivosinc.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
Log Message:
-----------
OvmfPkg/RiscVVirt: Configure zkr PCD for Virt
Keep ZKR feature disabled by default until HW supports
it. Feature is implemented in RISC-V BaseRngLib.
Cc: Andrei Warkentin <andrei.warken...@intel.com>
Cc: Ard Biesheuvel <ardb+tianoc...@kernel.org>
Cc: Gerd Hoffmann <kra...@redhat.com>
Cc: Jiewen Yao <jiewen....@intel.com>
Cc: Sunil V L <suni...@ventanamicro.com>
Signed-off-by: Dhaval Sharma <dha...@rivosinc.com>
Co-authored-by: Tim Wawrzynczak <t...@rivosinc.com>
Compare: https://github.com/tianocore/edk2/compare/d4dbe5e101dc...91226e1eecac
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