Branch: refs/heads/master
Home: https://github.com/tianocore/edk2
Commit: c1eb477e0629e3a444cab43c66a02fb8daf12ce9
https://github.com/tianocore/edk2/commit/c1eb477e0629e3a444cab43c66a02fb8daf12ce9
Author: Ceping Sun <cepingx....@intel.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M OvmfPkg/TdxDxe/X64/ApRunLoop.nasm
Log Message:
-----------
OvmfPkg/TdxDxe: Clear GPR Mask for RBX
Refer to intel-tdx-module-api spec section 5.5.21, GPR mask
(TDVMCALL_EXPOSE_REGS_MASK) is a bitmap that controls which
part of the guest TD GPR and XMM state is passed as-is to
the VMM and back.
- A bit value of 0 indicates that the corresponding register
is saved by the Intel TDX module and not passed as-is to
Host VMM.
- A bit value of 1 indicates that the corresponding register
is passed as-is to the host VMM.
Currently, RBX is used as the mailbox address in ApRunLoop.nasm,
the corresponding bit value of RBX in MASK(Bit 3) is set as 1 which
means the value is passed to Host VMM as-is and it can be changed by
Host VMM.
So the bitmask shall be set as 0 to avoid this situation.
Reference:
[TDX-API]: intel-tdx-module-abi-spec
https://cdrdv2.intel.com/v1/dl/getContent/733579
Cc: Erdem Aktas <erdemak...@google.com>
Cc: Jiewen Yao <jiewen....@intel.com>
Cc: Min Xu <min.m...@intel.com>
Cc: Gerd Hoffmann <kra...@redhat.com>
Cc: Hunter Adrian <adrian.hun...@intel.com>
Signed-off-by: Ceping Sun <cepingx....@intel.com>
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