Branch: refs/heads/master
Home: https://github.com/tianocore/edk2
Commit: 48fa937f46db100cbb9667bce1d522dc178a192b
https://github.com/tianocore/edk2/commit/48fa937f46db100cbb9667bce1d522dc178a192b
Author: Dongyan Qian <[email protected]>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M OvmfPkg/LoongArchVirt/Library/ResetSystemAcpiLib/DxeResetSystemAcpiGed.c
M
OvmfPkg/LoongArchVirt/Library/ResetSystemAcpiLib/DxeResetSystemAcpiGedLib.inf
Log Message:
-----------
OvmfPkg/LoongArchVirt: Fix ACPI table walk in reset library
The DXE ACPI GED reset library locates the FADT by walking the
RSDT and XSDT from the RSDP. The existing code assumed that both
RSDP address fields were non-zero and that every table entry was a
valid ACPI table address.
That assumption is unsafe once NULL pointer detection is enabled. A
zero RSDT/XSDT address, or a zero table entry, can be converted into a
pointer to address 0 and then dereferenced while checking the table
signature.
RSDT entries are 32-bit physical addresses, while XSDT entries are
64-bit physical addresses. Parse those entry arrays separately so the
XSDT path does not split each 64-bit entry into two bogus 32-bit
values. Use ReadUnaligned64() for XSDT entries because the ACPI table
header size does not guarantee natural 8-byte alignment for the entry
array on all architectures.
Update the FADT discovery path to:
- skip RSDT scanning when RsdtAddress is zero,
- skip XSDT scanning when XsdtAddress is zero,
- ignore zero RSDT/XSDT entries,
- parse XSDT entries as UINT64 addresses, and
- read XSDT entries with unaligned-safe access.
This prevents the reset library from dereferencing address 0 while
preserving the existing behavior of using the first FADT found through
RSDT or XSDT.
Signed-off-by: Dongyan Qian <[email protected]>
Commit: f17ed80f61487a19271c218f7b569163e83d26eb
https://github.com/tianocore/edk2/commit/f17ed80f61487a19271c218f7b569163e83d26eb
Author: Dongyan Qian <[email protected]>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M UefiCpuPkg/CpuDxe/LoongArch64/CpuDxe.c
M UefiCpuPkg/Library/CpuMmuLib/LoongArch64/CpuMmu.c
Log Message:
-----------
UefiCpuPkg/LoongArch64: Support NULL pointer detection
Add the LoongArch64 CPU-side support needed to make NULL pointer
detection effective after DXE page tables are established.
The platform memory map can reserve page 0, but DXE still needs the
CPU/MMU layer to enforce the requested memory attribute. Apply
EFI_MEMORY_RP to virtual address 0 after the CPU Arch protocol is
installed when PcdNullPointerDetectionPropertyMask BIT0 is enabled.
This updates the active DXE mapping after GCD setup.
Also update the LoongArch64 page-table attribute conversion path so a
requested no-read mapping clears PAGE_VALID. On the tested
LoongArchVirt/QEMU path, the no-read attribute alone does not reliably
raise a load fault for VA 0. Invalidating the PTE makes an assembly
load from address 0 raise a page-invalid load exception instead of
silently reading through the mapping.
This commit only changes the common LoongArch64 CPU/MMU support. The
LoongArchVirt platform memory-map policy is updated separately.
Signed-off-by: Dongyan Qian <[email protected]>
Compare: https://github.com/tianocore/edk2/compare/22831880dc5d...f17ed80f6148
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