On 19 August 2015 at 12:47, Leif Lindholm <leif.lindh...@linaro.org> wrote: > On Wed, Aug 19, 2015 at 11:51:46AM +0200, Ard Biesheuvel wrote: >> No platforms use the ARMv6 (ARM11) support code anymore. In fact, the >> only reference to it in ArmPkg.dsc was commented out by Andrew in SVN >> r11298 (2011-02-03) so it may well be broken. So remove it. > > 48h have passed. > Reviewed-by: Leif Lindholm <leif.lindh...@linaro.org> >
Thanks Committed as SVN r18237 -- Ard. >> Contributed-under: TianoCore Contribution Agreement 1.0 >> Signed-off-by: Ard Biesheuvel <ard.biesheu...@linaro.org> >> --- >> v2: remove more outdated '#ifdef ARM_CPU_ARMv6' from ArmLib >> >> ArmPkg/ArmPkg.dsc | 4 - >> ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Lib.c | 37 --- >> ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11MpCoreLib.inf | 32 --- >> ArmPkg/Include/Library/ArmLib.h | 6 +- >> ArmPkg/Library/ArmLib/Arm11/Arm11Lib.c | 49 ---- >> ArmPkg/Library/ArmLib/Arm11/Arm11Lib.inf | 50 ---- >> ArmPkg/Library/ArmLib/Arm11/Arm11LibMem.c | 135 ---------- >> ArmPkg/Library/ArmLib/Arm11/Arm11LibPrePi.inf | 50 ---- >> ArmPkg/Library/ArmLib/Arm11/Arm11LibSec.inf | 46 ---- >> ArmPkg/Library/ArmLib/Arm11/Arm11Support.S | 257 >> -------------------- >> ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm | 157 >> ------------ >> ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S | 6 - >> ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm | 6 - >> 13 files changed, 1 insertion(+), 834 deletions(-) >> >> diff --git a/ArmPkg/ArmPkg.dsc b/ArmPkg/ArmPkg.dsc >> index 10e8a1a83d46..1237eed65953 100644 >> --- a/ArmPkg/ArmPkg.dsc >> +++ b/ArmPkg/ArmPkg.dsc >> @@ -152,10 +152,6 @@ [Components.ARM] >> ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf >> ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.inf >> >> -# ArmPkg/Library/ArmLib/Arm11/Arm11ArmLib.inf >> -# ArmPkg/Library/ArmLib/Arm11/Arm11ArmLibPrePi.inf >> -# ArmPkg/Library/ArmLib/Arm9/Arm9ArmLib.inf >> -# ArmPkg/Library/ArmLib/Arm9/Arm9ArmLibPrePi.inf >> ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf >> ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf >> >> diff --git a/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Lib.c >> b/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Lib.c >> deleted file mode 100644 >> index a08b7b1aee3f..000000000000 >> --- a/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Lib.c >> +++ /dev/null >> @@ -1,37 +0,0 @@ >> -/** @file >> - >> - Copyright (c) 2011-2012, ARM Limited. All rights reserved. >> - >> - This program and the accompanying materials >> - are licensed and made available under the terms and conditions of the BSD >> License >> - which accompanies this distribution. The full text of the license may be >> found at >> - http://opensource.org/licenses/bsd-license.php >> - >> - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, >> - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR >> IMPLIED. >> - >> -**/ >> - >> -#include <Base.h> >> -#include <Library/ArmLib.h> >> -#include <Library/ArmCpuLib.h> >> -#include <Library/IoLib.h> >> -#include <Library/PcdLib.h> >> - >> -VOID >> -ArmCpuSetup ( >> - IN UINTN MpId >> - ) >> -{ >> - ASSERT(0); //TODO: Implement me >> -} >> - >> - >> -VOID >> -ArmCpuSetupSmpNonSecure ( >> - IN UINTN MpId >> - ) >> -{ >> - ASSERT(0); //TODO: Implement me >> -} >> - >> diff --git a/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11MpCoreLib.inf >> b/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11MpCoreLib.inf >> deleted file mode 100644 >> index 3a796c19d0cc..000000000000 >> --- a/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11MpCoreLib.inf >> +++ /dev/null >> @@ -1,32 +0,0 @@ >> -#/* @file >> -# Copyright (c) 2011-2012, ARM Limited. All rights reserved. >> -# >> -# This program and the accompanying materials >> -# are licensed and made available under the terms and conditions of the >> BSD License >> -# which accompanies this distribution. The full text of the license may >> be found at >> -# http://opensource.org/licenses/bsd-license.php >> -# >> -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, >> -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR >> IMPLIED. >> -# >> -#*/ >> - >> -[Defines] >> - INF_VERSION = 0x00010005 >> - BASE_NAME = Arm11MpCoreLib >> - FILE_GUID = dc8a69e0-6be0-469c-94d3-5e6d71aa9808 >> - MODULE_TYPE = BASE >> - VERSION_STRING = 1.0 >> - LIBRARY_CLASS = ArmCpuLib >> - >> -[Packages] >> - MdePkg/MdePkg.dec >> - ArmPkg/ArmPkg.dec >> - >> -[LibraryClasses] >> - ArmLib >> - IoLib >> - PcdLib >> - >> -[Sources.common] >> - Arm11Lib.c >> diff --git a/ArmPkg/Include/Library/ArmLib.h >> b/ArmPkg/Include/Library/ArmLib.h >> index 9effb3eea9bf..c83a5a7f1b3c 100644 >> --- a/ArmPkg/Include/Library/ArmLib.h >> +++ b/ArmPkg/Include/Library/ArmLib.h >> @@ -19,11 +19,7 @@ >> #include <Uefi/UefiBaseType.h> >> >> #ifdef MDE_CPU_ARM >> - #ifdef ARM_CPU_ARMv6 >> - #include <Chipset/ARM1176JZ-S.h> >> - #else >> - #include <Chipset/ArmV7.h> >> - #endif >> + #include <Chipset/ArmV7.h> >> #elif defined(MDE_CPU_AARCH64) >> #include <Chipset/AArch64.h> >> #else >> diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.c >> b/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.c >> deleted file mode 100644 >> index 8c54b6cc8fd5..000000000000 >> --- a/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.c >> +++ /dev/null >> @@ -1,49 +0,0 @@ >> -/** @file >> - >> - Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> >> - Copyright (c) 2011 - 2014, ARM Limited. All rights reserved. >> - >> - This program and the accompanying materials >> - are licensed and made available under the terms and conditions of the BSD >> License >> - which accompanies this distribution. The full text of the license may be >> found at >> - http://opensource.org/licenses/bsd-license.php >> - >> - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, >> - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR >> IMPLIED. >> - >> -**/ >> - >> -#include <Chipset/ARM1176JZ-S.h> >> - >> -#include <Library/ArmLib.h> >> -#include <Library/DebugLib.h> >> -#include <Library/PcdLib.h> >> - >> -VOID >> -EFIAPI >> -ArmWriteVBar ( >> - IN UINTN VectorBase >> - ) >> -{ >> - ASSERT(FeaturePcdGet (PcdRelocateVectorTable) == TRUE); >> - >> - if (VectorBase == 0x0) { >> - ArmSetLowVectors (); >> - } else if (VectorBase == 0xFFFF0000) { >> - ArmSetHighVectors (); >> - } else { >> - // Feature not supported by ARM11. The Vector Table is either at 0x0 or >> 0xFFFF0000 >> - ASSERT(0); >> - } >> -} >> - >> -UINTN >> -EFIAPI >> -ArmReadVBar ( >> - VOID >> - ) >> -{ >> - ASSERT((FeaturePcdGet (PcdRelocateVectorTable) == TRUE) && ((PcdGet32 >> (PcdCpuVectorBaseAddress) == 0x0) || (PcdGet32 (PcdCpuVectorBaseAddress) == >> 0xFFFF0000))); >> - return PcdGet32 (PcdCpuVectorBaseAddress); >> -} >> - >> diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.inf >> b/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.inf >> deleted file mode 100644 >> index 6ac74d985c78..000000000000 >> --- a/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.inf >> +++ /dev/null >> @@ -1,50 +0,0 @@ >> -#/** @file >> -# Semihosting serail port lib >> -# >> -# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> >> -# >> -# This program and the accompanying materials >> -# are licensed and made available under the terms and conditions of the >> BSD License >> -# which accompanies this distribution. The full text of the license may be >> found at >> -# http://opensource.org/licenses/bsd-license.php >> -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, >> -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR >> IMPLIED. >> -# >> -# >> -#**/ >> - >> -[Defines] >> - INF_VERSION = 0x00010005 >> - BASE_NAME = Arm11ArmLib >> - FILE_GUID = 00586300-0E06-4790-AC44-86C56ACBB942 >> - MODULE_TYPE = DXE_DRIVER >> - VERSION_STRING = 1.0 >> - LIBRARY_CLASS = ArmLib >> - >> -[Sources.common] >> - ../Common/Arm/ArmLibSupport.S | GCC >> - ../Common/Arm/ArmLibSupport.asm | RVCT >> - ../Common/ArmLib.c >> - >> - Arm11Support.S | GCC >> - Arm11Support.asm | RVCT >> - >> - Arm11Lib.c >> - Arm11LibMem.c >> - ../Arm9/Arm9CacheInformation.c >> - >> -[Packages] >> - ArmPkg/ArmPkg.dec >> - MdePkg/MdePkg.dec >> - >> -[LibraryClasses] >> - MemoryAllocationLib >> - >> -[Protocols] >> - gEfiCpuArchProtocolGuid >> - >> -[FeaturePcd] >> - gArmTokenSpaceGuid.PcdRelocateVectorTable >> - >> -[FixedPcd] >> - gArmTokenSpaceGuid.PcdCpuVectorBaseAddress >> diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11LibMem.c >> b/ArmPkg/Library/ArmLib/Arm11/Arm11LibMem.c >> deleted file mode 100644 >> index 0f898015251d..000000000000 >> --- a/ArmPkg/Library/ArmLib/Arm11/Arm11LibMem.c >> +++ /dev/null >> @@ -1,135 +0,0 @@ >> -/** @file >> - >> - Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> >> - Copyright (c) 2011 - 2013, ARM Limited. All rights reserved. >> - >> - This program and the accompanying materials >> - are licensed and made available under the terms and conditions of the BSD >> License >> - which accompanies this distribution. The full text of the license may be >> found at >> - http://opensource.org/licenses/bsd-license.php >> - >> - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, >> - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR >> IMPLIED. >> - >> -**/ >> - >> -#include <Chipset/ARM1176JZ-S.h> >> -#include <Library/ArmLib.h> >> -#include <Library/BaseMemoryLib.h> >> -#include <Library/MemoryAllocationLib.h> >> - >> -VOID >> -FillTranslationTable ( >> - IN UINT32 *TranslationTable, >> - IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion >> - ) >> -{ >> - UINT32 *Entry; >> - UINTN Sections; >> - UINTN Index; >> - UINT32 Attributes; >> - UINT32 PhysicalBase = MemoryRegion->PhysicalBase; >> - >> - switch (MemoryRegion->Attributes) { >> - case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK: >> - Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0); >> - break; >> - case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH: >> - Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0); >> - break; >> - case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED: >> - Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0); >> - break; >> - case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK: >> - Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1); >> - break; >> - case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH: >> - Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1); >> - break; >> - case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED: >> - Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(1); >> - break; >> - default: >> - Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0); >> - break; >> - } >> - >> - Entry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, >> MemoryRegion->VirtualBase); >> - Sections = ((( MemoryRegion->Length - 1 ) / TT_DESCRIPTOR_SECTION_SIZE ) >> + 1 ); >> - >> - for (Index = 0; Index < Sections; Index++) >> - { >> - *Entry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | >> Attributes; >> - PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE; >> - } >> -} >> - >> -RETURN_STATUS >> -EFIAPI >> -ArmConfigureMmu ( >> - IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable, >> - OUT VOID **TranslationTableBase OPTIONAL, >> - OUT UINTN *TranslationTableSize OPTIONAL >> - ) >> -{ >> - VOID *TranslationTable; >> - >> - // Allocate pages for translation table. >> - TranslationTable = AllocatePages (EFI_SIZE_TO_PAGES >> (TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT)); >> - if (TranslationTable == NULL) { >> - return RETURN_OUT_OF_RESOURCES; >> - } >> - TranslationTable = (VOID *)(((UINTN)TranslationTable + >> TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK); >> - >> - if (TranslationTableBase != NULL) { >> - *TranslationTableBase = TranslationTable; >> - } >> - >> - if (TranslationTableBase != NULL) { >> - *TranslationTableSize = TRANSLATION_TABLE_SIZE; >> - } >> - >> - ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE); >> - >> - ArmCleanInvalidateDataCache(); >> - ArmInvalidateInstructionCache(); >> - ArmInvalidateTlb(); >> - >> - ArmDisableDataCache(); >> - ArmDisableInstructionCache(); >> - ArmDisableMmu(); >> - >> - // Make sure nothing sneaked into the cache >> - ArmCleanInvalidateDataCache(); >> - ArmInvalidateInstructionCache(); >> - >> - while (MemoryTable->Length != 0) { >> - FillTranslationTable(TranslationTable, MemoryTable); >> - MemoryTable++; >> - } >> - >> - ArmSetTTBR0(TranslationTable); >> - >> - ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) | >> - DOMAIN_ACCESS_CONTROL_NONE(14) | >> - DOMAIN_ACCESS_CONTROL_NONE(13) | >> - DOMAIN_ACCESS_CONTROL_NONE(12) | >> - DOMAIN_ACCESS_CONTROL_NONE(11) | >> - DOMAIN_ACCESS_CONTROL_NONE(10) | >> - DOMAIN_ACCESS_CONTROL_NONE( 9) | >> - DOMAIN_ACCESS_CONTROL_NONE( 8) | >> - DOMAIN_ACCESS_CONTROL_NONE( 7) | >> - DOMAIN_ACCESS_CONTROL_NONE( 6) | >> - DOMAIN_ACCESS_CONTROL_NONE( 5) | >> - DOMAIN_ACCESS_CONTROL_NONE( 4) | >> - DOMAIN_ACCESS_CONTROL_NONE( 3) | >> - DOMAIN_ACCESS_CONTROL_NONE( 2) | >> - DOMAIN_ACCESS_CONTROL_NONE( 1) | >> - DOMAIN_ACCESS_CONTROL_MANAGER(0)); >> - >> - ArmEnableInstructionCache(); >> - ArmEnableDataCache(); >> - ArmEnableMmu(); >> - >> - return RETURN_SUCCESS; >> -} >> diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11LibPrePi.inf >> b/ArmPkg/Library/ArmLib/Arm11/Arm11LibPrePi.inf >> deleted file mode 100644 >> index 239493d3e60d..000000000000 >> --- a/ArmPkg/Library/ArmLib/Arm11/Arm11LibPrePi.inf >> +++ /dev/null >> @@ -1,50 +0,0 @@ >> -#/** @file >> -# Semihosting serail port lib >> -# >> -# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> >> -# >> -# This program and the accompanying materials >> -# are licensed and made available under the terms and conditions of the >> BSD License >> -# which accompanies this distribution. The full text of the license may be >> found at >> -# http://opensource.org/licenses/bsd-license.php >> -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, >> -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR >> IMPLIED. >> -# >> -# >> -#**/ >> - >> -[Defines] >> - INF_VERSION = 0x00010005 >> - BASE_NAME = Arm11ArmLib >> - FILE_GUID = 8dfb4ea2-3901-44f9-ae54-ca3d50362d2f >> - MODULE_TYPE = DXE_DRIVER >> - VERSION_STRING = 1.0 >> - LIBRARY_CLASS = ArmLib >> - >> -[Sources.common] >> - ../Common/Arm/ArmLibSupport.S | GCC >> - ../Common/Arm/ArmLibSupport.asm | RVCT >> - ../Common/ArmLib.c >> - >> - Arm11Support.S | GCC >> - Arm11Support.asm | RVCT >> - >> - Arm11Lib.c >> - Arm11LibMem.c >> - ../Arm9/Arm9CacheInformation.c >> - >> -[Packages] >> - ArmPkg/ArmPkg.dec >> - MdePkg/MdePkg.dec >> - >> -[LibraryClasses] >> - PrePiLib >> - >> -[Protocols] >> - gEfiCpuArchProtocolGuid >> - >> -[FeaturePcd] >> - gArmTokenSpaceGuid.PcdRelocateVectorTable >> - >> -[FixedPcd] >> - gArmTokenSpaceGuid.PcdCpuVectorBaseAddress >> diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11LibSec.inf >> b/ArmPkg/Library/ArmLib/Arm11/Arm11LibSec.inf >> deleted file mode 100644 >> index ef3c8f8f72a4..000000000000 >> --- a/ArmPkg/Library/ArmLib/Arm11/Arm11LibSec.inf >> +++ /dev/null >> @@ -1,46 +0,0 @@ >> -#/** @file >> -# Semihosting serail port lib >> -# >> -# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> >> -# >> -# This program and the accompanying materials >> -# are licensed and made available under the terms and conditions of the >> BSD License >> -# which accompanies this distribution. The full text of the license may be >> found at >> -# http://opensource.org/licenses/bsd-license.php >> -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, >> -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR >> IMPLIED. >> -# >> -# >> -#**/ >> - >> -[Defines] >> - INF_VERSION = 0x00010005 >> - BASE_NAME = Arm11LibSec >> - FILE_GUID = bfecdbc7-a860-4993-bc09-8e3ea762a758 >> - MODULE_TYPE = BASE >> - VERSION_STRING = 1.0 >> - LIBRARY_CLASS = ArmLib >> - >> -[Sources.common] >> - ../Common/Arm/ArmLibSupport.S | GCC >> - ../Common/Arm/ArmLibSupport.asm | RVCT >> - ../Common/ArmLib.c >> - >> - Arm11Support.S | GCC >> - Arm11Support.asm | RVCT >> - >> - Arm11Lib.c >> - ../Arm9/Arm9CacheInformation.c >> - >> -[Packages] >> - ArmPkg/ArmPkg.dec >> - MdePkg/MdePkg.dec >> - >> -[Protocols] >> - gEfiCpuArchProtocolGuid >> - >> -[FeaturePcd] >> - gArmTokenSpaceGuid.PcdRelocateVectorTable >> - >> -[FixedPcd] >> - gArmTokenSpaceGuid.PcdCpuVectorBaseAddress >> diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11Support.S >> b/ArmPkg/Library/ArmLib/Arm11/Arm11Support.S >> deleted file mode 100644 >> index 25612f35ec63..000000000000 >> --- a/ArmPkg/Library/ArmLib/Arm11/Arm11Support.S >> +++ /dev/null >> @@ -1,257 +0,0 @@ >> -#------------------------------------------------------------------------------ >> -# >> -# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> >> -# Copyright (c) 2011, ARM Limited. All rights reserved. >> -# >> -# This program and the accompanying materials >> -# are licensed and made available under the terms and conditions of the BSD >> License >> -# which accompanies this distribution. The full text of the license may be >> found at >> -# http://opensource.org/licenses/bsd-license.php >> -# >> -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, >> -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR >> IMPLIED. >> -# >> -#------------------------------------------------------------------------------ >> - >> -#include <AsmMacroIoLib.h> >> - >> -.text >> -.align 2 >> -GCC_ASM_EXPORT(ArmDisableCachesAndMmu) >> -GCC_ASM_EXPORT(ArmCleanInvalidateDataCache) >> -GCC_ASM_EXPORT(ArmCleanDataCache) >> -GCC_ASM_EXPORT(ArmInvalidateDataCache) >> -GCC_ASM_EXPORT(ArmInvalidateInstructionCache) >> -GCC_ASM_EXPORT(ArmInvalidateDataCacheEntryByMVA) >> -GCC_ASM_EXPORT(ArmCleanDataCacheEntryByMVA) >> -GCC_ASM_EXPORT(ArmCleanInvalidateDataCacheEntryByMVA) >> -GCC_ASM_EXPORT(ArmEnableMmu) >> -GCC_ASM_EXPORT(ArmDisableMmu) >> -GCC_ASM_EXPORT(ArmMmuEnabled) >> -GCC_ASM_EXPORT(ArmEnableDataCache) >> -GCC_ASM_EXPORT(ArmDisableDataCache) >> -GCC_ASM_EXPORT(ArmEnableInstructionCache) >> -GCC_ASM_EXPORT(ArmDisableInstructionCache) >> -GCC_ASM_EXPORT(ArmEnableBranchPrediction) >> -GCC_ASM_EXPORT(ArmDisableBranchPrediction) >> -GCC_ASM_EXPORT(ArmDataMemoryBarrier) >> -GCC_ASM_EXPORT(ArmDataSyncronizationBarrier) >> -GCC_ASM_EXPORT(ArmInstructionSynchronizationBarrier) >> -GCC_ASM_EXPORT(ArmSetLowVectors) >> -GCC_ASM_EXPORT(ArmSetHighVectors) >> -GCC_ASM_EXPORT(ArmIsMpCore) >> -GCC_ASM_EXPORT(ArmCallWFI) >> -GCC_ASM_EXPORT(ArmReadMpidr) >> -GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry) >> -GCC_ASM_EXPORT(ArmEnableFiq) >> -GCC_ASM_EXPORT(ArmDisableFiq) >> -GCC_ASM_EXPORT(ArmEnableInterrupts) >> -GCC_ASM_EXPORT(ArmDisableInterrupts) >> -GCC_ASM_EXPORT (ArmEnableVFP) >> - >> -Arm11PartNumberMask: .word 0xFFF0 >> -Arm11PartNumber: .word 0xB020 >> - >> -.set DC_ON, (0x1<<2) >> -.set IC_ON, (0x1<<12) >> -.set XP_ON, (0x1<<23) >> -.set CTRL_M_BIT, (1 << 0) >> -.set CTRL_C_BIT, (1 << 2) >> -.set CTRL_I_BIT, (1 << 12) >> - >> -ASM_PFX(ArmDisableCachesAndMmu): >> - mrc p15, 0, r0, c1, c0, 0 @ Get control register >> - bic r0, r0, #CTRL_M_BIT @ Disable MMU >> - bic r0, r0, #CTRL_C_BIT @ Disable D Cache >> - bic r0, r0, #CTRL_I_BIT @ Disable I Cache >> - mcr p15, 0, r0, c1, c0, 0 @ Write control register >> - bx LR >> - >> -ASM_PFX(ArmInvalidateDataCacheEntryByMVA): >> - mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line >> - bx lr >> - >> - >> -ASM_PFX(ArmCleanDataCacheEntryByMVA): >> - mcr p15, 0, r0, c7, c10, 1 @clean single data cache line >> - bx lr >> - >> - >> -ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA): >> - mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache >> line >> - bx lr >> - >> - >> -ASM_PFX(ArmCleanDataCache): >> - mcr p15, 0, r0, c7, c10, 0 @ clean entire data cache >> - bx lr >> - >> - >> -ASM_PFX(ArmCleanInvalidateDataCache): >> - mcr p15, 0, r0, c7, c14, 0 @ clean and invalidate entire data cache >> - bx lr >> - >> - >> -ASM_PFX(ArmInvalidateDataCache): >> - mcr p15, 0, r0, c7, c6, 0 @ invalidate entire data cache >> - bx lr >> - >> - >> -ASM_PFX(ArmInvalidateInstructionCache): >> - mcr p15, 0, r0, c7, c5, 0 @invalidate entire instruction cache >> - mov R0,#0 >> - mcr p15,0,R0,c7,c5,4 @Flush Prefetch buffer >> - bx lr >> - >> -ASM_PFX(ArmEnableMmu): >> - mrc p15,0,R0,c1,c0,0 >> - orr R0,R0,#1 >> - mcr p15,0,R0,c1,c0,0 >> - bx LR >> - >> -ASM_PFX(ArmMmuEnabled): >> - mrc p15,0,R0,c1,c0,0 >> - and R0,R0,#1 >> - bx LR >> - >> -ASM_PFX(ArmDisableMmu): >> - mrc p15,0,R0,c1,c0,0 >> - bic R0,R0,#1 >> - mcr p15,0,R0,c1,c0,0 >> - mov R0,#0 >> - mcr p15,0,R0,c7,c10,4 @Data synchronization barrier >> - mov R0,#0 >> - mcr p15,0,R0,c7,c5,4 @Flush Prefetch buffer >> - bx LR >> - >> -ASM_PFX(ArmEnableDataCache): >> - LoadConstantToReg(DC_ON, R1) @ldr R1,=DC_ON >> - mrc p15,0,R0,c1,c0,0 @Read control register configuration data >> - orr R0,R0,R1 @Set C bit >> - mcr p15,0,r0,c1,c0,0 @Write control register configuration data >> - bx LR >> - >> -ASM_PFX(ArmDisableDataCache): >> - LoadConstantToReg(DC_ON, R1) @ldr R1,=DC_ON >> - mrc p15,0,R0,c1,c0,0 @Read control register configuration data >> - bic R0,R0,R1 @Clear C bit >> - mcr p15,0,r0,c1,c0,0 @Write control register configuration data >> - bx LR >> - >> -ASM_PFX(ArmEnableInstructionCache): >> - ldr R1,=IC_ON >> - mrc p15,0,R0,c1,c0,0 @Read control register configuration data >> - orr R0,R0,R1 @Set I bit >> - mcr p15,0,r0,c1,c0,0 @Write control register configuration data >> - bx LR >> - >> -ASM_PFX(ArmDisableInstructionCache): >> - ldr R1,=IC_ON >> - mrc p15,0,R0,c1,c0,0 @Read control register configuration data >> - bic R0,R0,R1 @Clear I bit. >> - mcr p15,0,r0,c1,c0,0 @Write control register configuration data >> - bx LR >> - >> -ASM_PFX(ArmEnableBranchPrediction): >> - mrc p15, 0, r0, c1, c0, 0 >> - orr r0, r0, #0x00000800 >> - mcr p15, 0, r0, c1, c0, 0 >> - bx LR >> - >> -ASM_PFX(ArmDisableBranchPrediction): >> - mrc p15, 0, r0, c1, c0, 0 >> - bic r0, r0, #0x00000800 >> - mcr p15, 0, r0, c1, c0, 0 >> - bx LR >> - >> -ASM_PFX(ArmDataMemoryBarrier): >> - mov R0, #0 >> - mcr P15, #0, R0, C7, C10, #5 >> - bx LR >> - >> -ASM_PFX(ArmDataSyncronizationBarrier): >> - mov R0, #0 >> - mcr P15, #0, R0, C7, C10, #4 >> - bx LR >> - >> -ASM_PFX(ArmInstructionSynchronizationBarrier): >> - mov R0, #0 >> - mcr P15, #0, R0, C7, C5, #4 >> - bx LR >> - >> -ASM_PFX(ArmSetLowVectors): >> - mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register >> configuration data) >> - bic r0, r0, #0x00002000 @ clear V bit >> - mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control >> register configuration data) >> - bx LR >> - >> -ASM_PFX(ArmSetHighVectors): >> - mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register >> configuration data) >> - orr r0, r0, #0x00002000 @ clear V bit >> - mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control >> register configuration data) >> - bx LR >> - >> -ASM_PFX(ArmIsMpCore): >> - push { r1 } >> - mrc p15, 0, r0, c0, c0, 0 >> - # Extract Part Number to check it is an ARM11MP core (0xB02) >> - LoadConstantToReg (Arm11PartNumberMask, r1) >> - and r0, r0, r1 >> - LoadConstantToReg (Arm11PartNumber, r1) >> - cmp r0, r1 >> - movne r0, #0 >> - pop { r1 } >> - bx lr >> - >> -ASM_PFX(ArmCallWFI): >> - wfi >> - bx lr >> - >> -ASM_PFX(ArmReadMpidr): >> - mrc p15, 0, r0, c0, c0, 5 @ read MPIDR >> - bx lr >> - >> -ASM_PFX(ArmEnableFiq): >> - mrs R0,CPSR >> - bic R0,R0,#0x40 @Enable FIQ interrupts >> - msr CPSR_c,R0 >> - bx LR >> - >> -ASM_PFX(ArmDisableFiq): >> - mrs R0,CPSR >> - orr R1,R0,#0x40 @Disable FIQ interrupts >> - msr CPSR_c,R1 >> - tst R0,#0x80 >> - moveq R0,#1 >> - movne R0,#0 >> - bx LR >> - >> -ASM_PFX(ArmEnableInterrupts): >> - mrs R0,CPSR >> - bic R0,R0,#0x80 @Enable IRQ interrupts >> - msr CPSR_c,R0 >> - bx LR >> - >> -ASM_PFX(ArmDisableInterrupts): >> - mrs R0,CPSR >> - orr R1,R0,#0x80 @Disable IRQ interrupts >> - msr CPSR_c,R1 >> - tst R0,#0x80 >> - moveq R0,#1 >> - movne R0,#0 >> - bx LR >> - >> -ASM_PFX(ArmEnableVFP): >> - # Read CPACR (Coprocessor Access Control Register) >> - mrc p15, 0, r0, c1, c0, 2 >> - # Enable VPF access (Full Access to CP10, CP11) (V* instructions) >> - orr r0, r0, #0x00f00000 >> - # Write back CPACR (Coprocessor Access Control Register) >> - mcr p15, 0, r0, c1, c0, 2 >> - # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled >> and operate normally. >> - mov r0, #0x40000000 >> - #TODO: Fixme - need compilation flag >> - #fmxr FPEXC, r0 >> - bx lr >> - >> -ASM_FUNCTION_REMOVE_IF_UNREFERENCED >> diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm >> b/ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm >> deleted file mode 100644 >> index 53283d1eea2a..000000000000 >> --- a/ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm >> +++ /dev/null >> @@ -1,157 +0,0 @@ >> -//------------------------------------------------------------------------------ >> -// >> -// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> >> -// >> -// This program and the accompanying materials >> -// are licensed and made available under the terms and conditions of the >> BSD License >> -// which accompanies this distribution. The full text of the license may >> be found at >> -// http://opensource.org/licenses/bsd-license.php >> -// >> -// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, >> -// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR >> IMPLIED. >> -// >> -//------------------------------------------------------------------------------ >> - >> - EXPORT ArmCleanInvalidateDataCache >> - EXPORT ArmCleanDataCache >> - EXPORT ArmInvalidateDataCache >> - EXPORT ArmInvalidateInstructionCache >> - EXPORT ArmInvalidateDataCacheEntryByMVA >> - EXPORT ArmCleanDataCacheEntryByMVA >> - EXPORT ArmCleanInvalidateDataCacheEntryByMVA >> - EXPORT ArmEnableMmu >> - EXPORT ArmDisableMmu >> - EXPORT ArmMmuEnabled >> - EXPORT ArmEnableDataCache >> - EXPORT ArmDisableDataCache >> - EXPORT ArmEnableInstructionCache >> - EXPORT ArmDisableInstructionCache >> - EXPORT ArmEnableBranchPrediction >> - EXPORT ArmDisableBranchPrediction >> - EXPORT ArmDataMemoryBarrier >> - EXPORT ArmDataSyncronizationBarrier >> - EXPORT ArmInstructionSynchronizationBarrier >> - >> - >> -DC_ON EQU ( 0x1:SHL:2 ) >> -IC_ON EQU ( 0x1:SHL:12 ) >> -XP_ON EQU ( 0x1:SHL:23 ) >> - >> - >> - AREA ArmCacheLib, CODE, READONLY >> - PRESERVE8 >> - >> - >> -ArmInvalidateDataCacheEntryByMVA >> - mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line >> - bx lr >> - >> - >> -ArmCleanDataCacheEntryByMVA >> - mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line >> - bx lr >> - >> - >> -ArmCleanInvalidateDataCacheEntryByMVA >> - mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache >> line >> - bx lr >> - >> - >> -ArmCleanDataCache >> - mcr p15, 0, r0, c7, c10, 0 ; clean entire data cache >> - bx lr >> - >> - >> -ArmCleanInvalidateDataCache >> - mcr p15, 0, r0, c7, c14, 0 ; clean and invalidate entire data cache >> - bx lr >> - >> - >> -ArmInvalidateDataCache >> - mcr p15, 0, r0, c7, c6, 0 ; invalidate entire data cache >> - bx lr >> - >> - >> -ArmInvalidateInstructionCache >> - mcr p15, 0, r0, c7, c5, 0 ;invalidate entire instruction cache >> - mov R0,#0 >> - mcr p15,0,R0,c7,c5,4 ;Flush Prefetch buffer >> - bx lr >> - >> -ArmEnableMmu >> - mrc p15,0,R0,c1,c0,0 >> - orr R0,R0,#1 >> - mcr p15,0,R0,c1,c0,0 >> - bx LR >> - >> -ArmMmuEnabled >> - mrc p15,0,R0,c1,c0,0 >> - and R0,R0,#1 >> - bx LR >> - >> -ArmDisableMmu >> - mrc p15,0,R0,c1,c0,0 >> - bic R0,R0,#1 >> - mcr p15,0,R0,c1,c0,0 >> - mov R0,#0 >> - mcr p15,0,R0,c7,c10,4 ;Data synchronization barrier >> - mov R0,#0 >> - mcr p15,0,R0,c7,c5,4 ;Flush Prefetch buffer >> - bx LR >> - >> -ArmEnableDataCache >> - LDR R1,=DC_ON >> - MRC p15,0,R0,c1,c0,0 ;Read control register configuration data >> - ORR R0,R0,R1 ;Set C bit >> - MCR p15,0,r0,c1,c0,0 ;Write control register configuration data >> - BX LR >> - >> -ArmDisableDataCache >> - LDR R1,=DC_ON >> - MRC p15,0,R0,c1,c0,0 ;Read control register configuration data >> - BIC R0,R0,R1 ;Clear C bit >> - MCR p15,0,r0,c1,c0,0 ;Write control register configuration data >> - BX LR >> - >> -ArmEnableInstructionCache >> - LDR R1,=IC_ON >> - MRC p15,0,R0,c1,c0,0 ;Read control register configuration data >> - ORR R0,R0,R1 ;Set I bit >> - MCR p15,0,r0,c1,c0,0 ;Write control register configuration data >> - BX LR >> - >> -ArmDisableInstructionCache >> - LDR R1,=IC_ON >> - MRC p15,0,R0,c1,c0,0 ;Read control register configuration data >> - BIC R0,R0,R1 ;Clear I bit. >> - MCR p15,0,r0,c1,c0,0 ;Write control register configuration data >> - BX LR >> - >> -ArmEnableBranchPrediction >> - mrc p15, 0, r0, c1, c0, 0 >> - orr r0, r0, #0x00000800 >> - mcr p15, 0, r0, c1, c0, 0 >> - bx LR >> - >> -ArmDisableBranchPrediction >> - mrc p15, 0, r0, c1, c0, 0 >> - bic r0, r0, #0x00000800 >> - mcr p15, 0, r0, c1, c0, 0 >> - bx LR >> - >> -ASM_PFX(ArmDataMemoryBarrier): >> - mov R0, #0 >> - mcr P15, #0, R0, C7, C10, #5 >> - bx LR >> - >> -ASM_PFX(ArmDataSyncronizationBarrier): >> - mov R0, #0 >> - mcr P15, #0, R0, C7, C10, #4 >> - bx LR >> - >> -ASM_PFX(ArmInstructionSynchronizationBarrier): >> - MOV R0, #0 >> - MCR P15, #0, R0, C7, C5, #4 >> - bx LR >> - >> - END >> diff --git a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S >> b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S >> index 43842f325e4e..59f991885995 100644 >> --- a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S >> +++ b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S >> @@ -15,12 +15,6 @@ >> >> #include <AsmMacroIoLib.h> >> >> -#ifdef ARM_CPU_ARMv6 >> -// No memory barriers for ARMv6 >> -#define isb >> -#define dsb >> -#endif >> - >> .text >> .align 2 >> GCC_ASM_EXPORT(ArmReadMidr) >> diff --git a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm >> b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm >> index 8864c1605668..0974d4608f75 100644 >> --- a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm >> +++ b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm >> @@ -17,12 +17,6 @@ >> >> INCLUDE AsmMacroIoLib.inc >> >> -#ifdef ARM_CPU_ARMv6 >> -// No memory barriers for ARMv6 >> -#define isb >> -#define dsb >> -#endif >> - >> EXPORT ArmReadMidr >> EXPORT ArmCacheInfo >> EXPORT ArmGetInterruptState >> -- >> 1.9.1 >> _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
