Per IA32 SDM, if CPUID.80000008H is not available, software may assume that the processor supports a 36-bit physical address size. However, for such old processors (For example, Quark processor), MtrrValidBitsMask and MtrrValidAddressMask values are reverted and wrong in MtrrLib. MtrrValidBitsMask should be 0xFFFFFFFFFULL and MtrrValidAddressMask should be 0xFFFFFF000ULL.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <[email protected]> CC: Feng Tian <[email protected]> CC: Jiewen Yao <[email protected]> --- UefiCpuPkg/Library/MtrrLib/MtrrLib.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c index d9449bc..a655605 100644 --- a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c +++ b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c @@ -1,7 +1,7 @@ /** @file MTRR setting library - Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR> + Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.<BR> This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -840,8 +840,8 @@ MtrrLibInitializeMtrrMask ( *MtrrValidBitsMask = LShiftU64 (1, PhysicalAddressBits) - 1; *MtrrValidAddressMask = *MtrrValidBitsMask & 0xfffffffffffff000ULL; } else { - *MtrrValidBitsMask = MTRR_LIB_CACHE_VALID_ADDRESS; - *MtrrValidAddressMask = 0xFFFFFFFF; + *MtrrValidBitsMask = MTRR_LIB_MSR_VALID_MASK; + *MtrrValidAddressMask = MTRR_LIB_CACHE_VALID_ADDRESS; } } -- 1.9.5.msysgit.0 _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
