Now that the AArch64 MMU code correctly identifies and handles
naturally aligned regions of more than 2 MB in size, it will happily
try to use block mappings at level 0 to map huge memory regions, such
as the single cacheable 1:1 mapping we use for Xen domU to map the
entire PA space. However, block mappings are not supported at level 0
so the resulting translation tables will be incorrect, causing
execution to fail as soon as the MMU is enabled.
So use level 1 as the minimum level at which to perform block
translations.
Reported-by: Julien Grall <julien.gr...@citrix.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
---
ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
b/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
index df37154f350d..b2ab5aa7bbc2 100644
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
@@ -295,8 +295,9 @@ GetBlockEntryListFromAddress (
BaseAddressAlignment = LowBitSet64 (RegionStart);
}
- // Identify the Page Level the RegionStart must belongs to
- PageLevel = 3 - ((BaseAddressAlignment - 12) / 9);
+ // Identify the Page Level the RegionStart must belong to. Note that
PageLevel
+ // should be at least 1 since block translations are not supported at level 0
+ PageLevel = MAX (3 - ((BaseAddressAlignment - 12) / 9), 1);
// If the required size is smaller than the current block size then we need
to go to the page below.
// The PageLevel was calculated on the Base Address alignment but did not
take in account the alignment
--
1.9.1
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