On Mon, Sep 21, 2015 at 04:02:23PM -0700, Ard Biesheuvel wrote: > All our page tables are allocated from memory whose cacheability > attributes are inherited by the cacheability bits in the MMU control > register, so there is no need for explicit cache maintenance after > updating the page tables. And even if there were, Set/Way operations > are not appropriate anyway for ensuring that these changes make it to > main memory. So just remove the explicit cache maintenance completely. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Ard Biesheuvel <[email protected]> > --- > ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c | 6 ------ > 1 file changed, 6 deletions(-) > > diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c > b/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c > index c6da461dd5bb..e7320e543c7f 100644 > --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c > +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c > @@ -504,12 +504,6 @@ SetMemoryAttributes ( > return Status; > } > > - // Flush d-cache so descriptors make it back to uncached memory for > subsequent table walks > - // flush and invalidate pages > - ArmCleanInvalidateDataCache (); > - > - ArmInvalidateInstructionCache (); > -
Yeah, this looks like a plain copy from the 32-bit code (where it is needed ... although I'm not convinced this is the correct operation even for 32-bit - need to revisit). This can be pushed independent of the series. Reviewed-by: Leif Lindholm <[email protected]> > // Invalidate all TLB entries so changes are synced > ArmInvalidateTlb (); > > -- > 1.9.1 > _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
