From: Paolo Bonzini <pbonz...@redhat.com>
The descriptor format is different and the assembly source is
converted to nasm, but otherwise there is no difference.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
---
Notes:
v3:
- new in v3
OvmfPkg/QuarkPort/CpuS3DataDxe/CpuS3DataDxe.inf | 5 +
OvmfPkg/QuarkPort/CpuS3DataDxe/X64/ArchSpecificDef.h | 59 +++++++++++
OvmfPkg/QuarkPort/CpuS3DataDxe/X64/ArchSpecific.c | 108 ++++++++++++++++++++
OvmfPkg/QuarkPort/CpuS3DataDxe/X64/CpuAsm.nasm | 58 +++++++++++
4 files changed, 230 insertions(+)
diff --git a/OvmfPkg/QuarkPort/CpuS3DataDxe/CpuS3DataDxe.inf
b/OvmfPkg/QuarkPort/CpuS3DataDxe/CpuS3DataDxe.inf
index 2610a63..4bec056 100644
--- a/OvmfPkg/QuarkPort/CpuS3DataDxe/CpuS3DataDxe.inf
+++ b/OvmfPkg/QuarkPort/CpuS3DataDxe/CpuS3DataDxe.inf
@@ -63,6 +63,11 @@ [Sources.Ia32]
IA32/ArchSpecificDef.h
IA32/ArchSpecific.c
+[Sources.X64]
+ X64/CpuAsm.nasm
+ X64/ArchSpecificDef.h
+ X64/ArchSpecific.c
+
[Packages]
MdePkg/MdePkg.dec
IntelFrameworkPkg/IntelFrameworkPkg.dec
diff --git a/OvmfPkg/QuarkPort/CpuS3DataDxe/X64/ArchSpecificDef.h
b/OvmfPkg/QuarkPort/CpuS3DataDxe/X64/ArchSpecificDef.h
new file mode 100644
index 0000000..5ea4cf6
--- /dev/null
+++ b/OvmfPkg/QuarkPort/CpuS3DataDxe/X64/ArchSpecificDef.h
@@ -0,0 +1,59 @@
+/** @file
+
+Copyright (C) 2015, Red Hat, Inc.
+Copyright (c) 2013-2015 Intel Corporation.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions
+are met:
+
+* Redistributions of source code must retain the above copyright
+notice, this list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+* Neither the name of Intel Corporation nor the names of its
+contributors may be used to endorse or promote products derived
+from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+Module Name:
+
+ ProcessorDef.h
+
+Abstract:
+
+ Definition for X64 processor
+
+**/
+
+#ifndef _PROCESSOR_DEF_H_
+#define _PROCESSOR_DEF_H_
+
+#pragma pack(1)
+
+typedef struct {
+ UINT16 OffsetLow;
+ UINT16 SegmentSelector;
+ UINT16 Attributes;
+ UINT16 OffsetHigh;
+ UINT32 OffsetUpper;
+ UINT32 Zero;
+} INTERRUPT_GATE_DESCRIPTOR;
+
+#pragma pack()
+
+#endif
diff --git a/OvmfPkg/QuarkPort/CpuS3DataDxe/X64/ArchSpecific.c
b/OvmfPkg/QuarkPort/CpuS3DataDxe/X64/ArchSpecific.c
new file mode 100644
index 0000000..544816d
--- /dev/null
+++ b/OvmfPkg/QuarkPort/CpuS3DataDxe/X64/ArchSpecific.c
@@ -0,0 +1,108 @@
+/** @file
+
+ Memory Operation Functions for IA32 Architecture.
+
+ Copyright (C) 2015, Red Hat, Inc.
+ Copyright (c) 2013-2015 Intel Corporation.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Intel Corporation nor the names of its
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ Module Name: ArchSpecific.c
+
+**/
+
+#include "Cpu.h"
+#include "MpService.h"
+
+//
+// OVMF port note: in this driver we don't actually use this buffer for
+// communicating between the BSP and the APs, we only allocate it as auxiliary
+// storage between the entry point and the EFI_SMM_CONFIGURATION_PROTOCOL
+// installation callback, for setting up various parameters of the AP startup
+// vector that is to be used by PiSmmCpuDxeSmm.
+//
+STATIC
+MP_CPU_EXCHANGE_INFO mExchangeInfoBuffer;
+MP_CPU_EXCHANGE_INFO *mExchangeInfo = &mExchangeInfoBuffer;
+
+/**
+ Prepares Startup Vector for APs.
+
+ This function prepares Startup Vector for APs.
+
+**/
+VOID
+PrepareAPStartupVector (
+ VOID
+ )
+{
+ //
+ // Allocate a 4K-aligned region under 1M for startup vector for AP.
+ // The region contains AP startup code and exchange data between BSP and AP.
+ //
+ AllocateStartupVector (SIZE_4KB);
+
+ //
+ // Get the start address of exchange data between BSP and AP.
+ //
+ ZeroMem ((VOID *) mExchangeInfo, sizeof (MP_CPU_EXCHANGE_INFO));
+
+ PrepareGdtIdtForAP (
+ (IA32_DESCRIPTOR *) (UINTN) &mExchangeInfo->GdtrProfile,
+ (IA32_DESCRIPTOR *) (UINTN) &mExchangeInfo->IdtrProfile
+ );
+}
+
+/**
+ Sets specified IDT entry with given function pointer.
+
+ This function sets specified IDT entry with given function pointer.
+
+ @param FunctionPointer Function pointer for IDT entry.
+ @param IdtEntry The IDT entry to update.
+
+ @return The original IDT entry value.
+
+**/
+UINTN
+SetIdtEntry (
+ IN UINTN FunctionPointer,
+ OUT INTERRUPT_GATE_DESCRIPTOR *IdtEntry
+)
+{
+ UINTN OriginalEntry;
+
+ OriginalEntry = IdtEntry->OffsetLow;
+ OriginalEntry |= ((UINTN) IdtEntry->OffsetHigh) << 16;
+ OriginalEntry |= ((UINTN) IdtEntry->OffsetUpper) << 32;
+
+ IdtEntry->OffsetLow = (UINT16) FunctionPointer;
+ IdtEntry->OffsetHigh = (UINT16) (FunctionPointer >> 16);
+ IdtEntry->OffsetUpper = (UINT32) (FunctionPointer >> 32);
+
+ return OriginalEntry;
+}
diff --git a/OvmfPkg/QuarkPort/CpuS3DataDxe/X64/CpuAsm.nasm
b/OvmfPkg/QuarkPort/CpuS3DataDxe/X64/CpuAsm.nasm
new file mode 100644
index 0000000..85502ae
--- /dev/null
+++ b/OvmfPkg/QuarkPort/CpuS3DataDxe/X64/CpuAsm.nasm
@@ -0,0 +1,58 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (C) 2015, Red Hat, Inc.
+; Copyright (c) 2013-2015 Intel Corporation.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions
+; are met:
+;
+; * Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+; * Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in
+; the documentation and/or other materials provided with the
+; distribution.
+; * Neither the name of Intel Corporation nor the names of its
+; contributors may be used to endorse or promote products derived
+; from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+; Module Name:
+;
+; CpuAsm.asm
+;
+; Abstract:
+;
+; Assembly code that supports X64 CPU architectural protocol
+;
+;------------------------------------------------------------------------------
+
+SECTION .text
+BITS 64
+
+global ASM_PFX(ApMachineCheckHandler)
+ASM_PFX(ApMachineCheckHandler):
+ ;
+ ; Clear MCIP flag of IA32_MCG_STATUS register
+ ;
+ mov ecx, 17ah
+ rdmsr
+ btr eax, 2
+ wrmsr
+
+ iretq
+
+global ASM_PFX(ApMachineCheckHandlerEnd)
+ASM_PFX(ApMachineCheckHandlerEnd):
--
1.8.3.1
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