Add support for the reading and writing MSR_SMM_FEATURE_CONTROL through the SmmCpuFeaturesIsSmmRegisterSupported(), SmmCpuFeaturesGetSmmRegister(), and SmmCpuFeaturesSetSmmRegister() functions. This MSR is supported if the Family/Model is 06_3C, 06_45, or 06_46.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <[email protected]> CC: Yao, Jiewen <[email protected]> CC: Jeff Fan <[email protected]> --- .../Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c index 4f2f9b6..0c1610d 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c @@ -31,17 +31,23 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. #define SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK 0x1F3 #define SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE 0x0A0 #define SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK 0x0A1 #define EFI_MSR_SMRR_MASK 0xFFFFF000 #define EFI_MSR_SMRR_PHYS_MASK_VALID BIT11 +#define SMM_FEATURES_LIB_SMM_FEATURE_CONTROL 0x4E0 // // Set default value to assume SMRR is not supported // BOOLEAN mSmrrSupported = FALSE; // +// Set default value to assume MSR_SMM_FEATURE_CONTROL is not supported +// +BOOLEAN mSmmFeatureControlSupported = FALSE; + +// // Set default value to assume IA-32 Architectural MSRs are used // UINT32 mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE; UINT32 mSmrrPhysMaskMsr = SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK; @@ -125,10 +131,24 @@ SmmCpuFeaturesLibConstructor ( } } // // Intel(R) 64 and IA-32 Architectures Software Developer's Manual + // Volume 3C, Section 35.10.1 MSRs in 4th Generation Intel(R) Core(TM) + // Processor Family + // + // If CPU Family/Model is 06_3C, 06_45, or 06_46 then use 4th Generation + // Intel(R) Core(TM) Processor Family MSRs + // + if (FamilyId == 0x06) { + if (ModelId == 0x3C || ModelId == 0x45 || ModelId == 0x46) { + mSmmFeatureControlSupported = TRUE; + } + } + + // + // Intel(R) 64 and IA-32 Architectures Software Developer's Manual // Volume 3C, Section 34.4.2 SMRAM Caching // An IA-32 processor does not automatically write back and invalidate its // caches before entering SMM or before exiting SMM. Because of this behavior, // care must be taken in the placement of the SMRAM in system memory and in // the caching of the SMRAM to prevent cache incoherence when switching back @@ -455,10 +475,13 @@ EFIAPI SmmCpuFeaturesIsSmmRegisterSupported ( IN UINTN CpuIndex, IN SMM_REG_NAME RegName ) { + if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) { + return TRUE; + } return FALSE; } /** Returns the current value of the SMM register for the specified CPU. @@ -477,10 +500,13 @@ EFIAPI SmmCpuFeaturesGetSmmRegister ( IN UINTN CpuIndex, IN SMM_REG_NAME RegName ) { + if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) { + return AsmReadMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL); + } return 0; } /** Sets the value of an SMM register on a specified CPU. @@ -499,10 +525,13 @@ SmmCpuFeaturesSetSmmRegister ( IN UINTN CpuIndex, IN SMM_REG_NAME RegName, IN UINT64 Value ) { + if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) { + AsmWriteMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL, Value); + } } /** Read an SMM Save State register on the target processor. If this function returns EFI_UNSUPPORTED, then the caller is responsible for reading the -- 1.9.5.msysgit.1 _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
