On Tue, Nov 03, 2015 at 11:16:32AM +0100, Ard Biesheuvel wrote: > There is no need to issue a full data synchronization barrier and an > instruction synchronization barrier after each and every set/way or > MVA cache maintenance operation. For the set/way case, we can simply > remove them, since the set/way outer loop already issues the required > barriers after completing its traversal over all the cache levels. > > For the MVA case, move the data synchronization barrier out of the > loop, and add the instruction synchronization barrier to the I-cache > invalidation by MVA routine. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Ard Biesheuvel <[email protected]> > --- > ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c | 2 ++ > ArmPkg/Library/ArmLib/AArch64/AArch64Support.S | 12 > ------------ > ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S | 12 > ------------ > ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm | 12 > ------------ > 4 files changed, 2 insertions(+), 36 deletions(-) > > diff --git a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c > b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c > index d8e53df6096e..175d29496c32 100644 > --- a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c > +++ b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c > @@ -35,6 +35,7 @@ CacheRangeOperation ( > LineOperation(AlignedAddress); > AlignedAddress += ArmCacheLineLength; > } > + ArmDataSynchronizationBarrier (); > } > > VOID > @@ -65,6 +66,7 @@ InvalidateInstructionCacheRange ( > { > CacheRangeOperation (Address, Length, ArmCleanDataCacheEntryByMVA); > ArmInvalidateInstructionCache (); > + ArmInstructionSynchronizationBarrier (); > return Address; > }
I've just spotted that the ArmInvalidateInstructionCache implementations already have the requisite DSB; ISB sequence, so we didn't actually need to introduce an ISB here. I don't know if it's best to remove the ISB here, or move both the DSB and ISB here for consistency across all the cache maintenance primitives. Either way, with that fixed up: Reviewed-by: Mark Rutland <[email protected]> Mark. _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
