On 03/11/2015 20:42, Jordan Justen wrote:
> On 2015-11-03 05:45:52, Paolo Bonzini wrote:
>>
>>
>> On 03/11/2015 14:25, Laszlo Ersek wrote:
>>>       - Agreement between Paolo, Jordan and Mike about implementing
>>>         broadcast SMIs. I am willing to code up whatever design is
>>>         agreed upon. Can everyone involved please prioritize this
>>>         discussion a little?
> 
> Obviously we'll have to follow what QEMU decides, so I'm not sure how
> much we can actually influence this.
> 
> Aside from the desire to better emulate chipset/platform designs of
> the actual hardware, I do have a related question.
> 
> If we use the local apic to initiate IPIs to other processors, what
> impact might that have on the state of the local apic if the OS is
> also trying to use it? For example, what if the OS is in the middle of
> trying to send an IPI?

A sequence like

   write to ICR
   out to 0xb2
   write to ICR2

is invalid.

On the other hand, the state of the _destination_ APICs is unaffected by
any IPIs that are delivered between writes to ICR and ICR2.

So it's okay to use the APIC from SMM, as long as it's only done on the
processor that received the synchronous SMI.

> Since it involves multiple projects, could it take longer to
> coordinate a change?

Perhaps, but on the other hand it's just the final 1%.  It's worthless
if we do not have the rest.

Paolo
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