Hi, The comments in https://github.com/mdkinney/edk2/blob/AddSmmUefiCpuPkg/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c show an example of how CPU save state and SMI hanlder are tiled in SMRAM, but I cannot find where is the save state for CPU m+2 to 2m. Besides, I cannot tell the relation between the processor number of the CPU save state and the processor number of SMI handler in each 32KB area. Can someone clarify this for me?
Comments are copied below: // +-----------------------------+ <-- 2^n offset from Base of allocated buffer // | CPU m+1 Save State | // +-----------------------------+ // | CPU m+1 Extra Data | // +-----------------------------+ // | Padding | // +-----------------------------+ // | CPU 2m SMI Entry | // +#############################+ <-- Base of allocated buffer + 64 KB // | CPU m-1 Save State | // +-----------------------------+ // | CPU m-1 Extra Data | // +-----------------------------+ // | Padding | // +-----------------------------+ // | CPU 2m-1 SMI Entry | // +=============================+ <-- 2^n offset from Base of allocated buffer // | . . . . . . . . . . . . | // +=============================+ <-- 2^n offset from Base of allocated buffer // | CPU 2 Save State | // +-----------------------------+ // | CPU 2 Extra Data | // +-----------------------------+ // | Padding | // +-----------------------------+ // | CPU m+1 SMI Entry | // +=============================+ <-- Base of allocated buffer + 32 KB // | CPU 1 Save State | // +-----------------------------+ // | CPU 1 Extra Data | // +-----------------------------+ // | Padding | // +-----------------------------+ // | CPU m SMI Entry | // +#############################+ <-- Base of allocated buffer + 32 KB == CPU 0 SMBASE + 64 KB // | CPU 0 Save State | // +-----------------------------+ // | CPU 0 Extra Data | // +-----------------------------+ // | Padding | // +-----------------------------+ // | CPU m-1 SMI Entry | // +=============================+ <-- 2^n offset from Base of allocated buffer // | . . . . . . . . . . . . | // +=============================+ <-- 2^n offset from Base of allocated buffer // | Padding | // +-----------------------------+ // | CPU 1 SMI Entry | // +=============================+ <-- 2^n offset from Base of allocated buffer // | Padding | // +-----------------------------+ // | CPU 0 SMI Entry | // +#############################+ <-- Base of allocated buffer == CPU 0 SMBASE + 32 KB Thanks, -- Anh Luong _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
