'PcdNormalMemoryNonshareableOverride' - that's what I am using now but it's still interesting to know what causes this effect. Thx for clearing this up.
Michael. On Tue, Nov 24, 2015 at 5:59 PM, Ard Biesheuvel <[email protected]> wrote: > On 24 November 2015 at 14:49, Michael Zimmermann > <[email protected]> wrote: > > sry for the late answer. > > > > The value of this register is: 0x10211103 > > I hope that helps. > > > > Thanks. > > This value decodes as; > InnerShr, bits [31:28] == 1, Implemented with hardware coherency support. > ShareLvl, bits [15:12] == 1, Two levels of shareability implemented. > OuterShr, bits [11: 8] == 1, Implemented with hardware coherency support. > > So the performance regression you are seeing is most likely caused by > the fact that the L2 or other bits of the coherency hardware (CCI?) > are not configured yet, or configured incorrectly. > > Note that I introduced a new feature PCD > 'PcdNormalMemoryNonshareableOverride' that reverts to the old > behavior. > > Regards, > Ard. > > > > On Wed, Nov 18, 2015 at 12:16 PM, Ard Biesheuvel < > [email protected]> > > wrote: > >> > >> On 16 November 2015 at 16:03, Michael Zimmermann > >> <[email protected]> wrote: > >> > Unfortunately I can't tell you much about how the L2 works or if it's > >> > configurable because it's a proprietary hw(I'm a opensource dev > working > >> > with > >> > Qualcomm Android devices). > >> > > >> > Also, I'm using ARM PrePi so EDK2 doesn't configure any architectural > hw > >> > besides exceptions and MMU. > >> > > >> > >> OK, I understand. > >> > >> I'd be interested in the contents of your ID_MMFR0 register > >> > >> MRC p15, 0, <Rt>, c0, c1, 4 ; Read ID_MMFR0 into Rt > >> > >> Could you please run that and reply with the result? > >> > >> Thanks, > >> Ard. > > > > > _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
