The attached python script was discarded by the mail server so here it is in plaintext for anyone interested.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <[email protected]> ## @file # asmfix.py: Process RVCT ASM files to replace exported functions with a # macro that includes AREA directives to enable code size reduction. # # Copyright (c) 2015 HP Development Company, L.P. # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BSD License # which accompanies this distribution. The full text of the license may be found at # http://opensource.org/licenses/bsd-license.php # # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. # import re import os import sys import glob gAreaPattern=re.compile('\s+AREA\s+(\w+)') gExportPattern=re.compile('\s+EXPORT\s+(\w+)') gLabelPattern=re.compile('^\w+') def ProcessFiles(files): print "processing files: %s" % files for file in files: ProcessFile(file) return def ProcessFile(fname): outfname = fname + '.new' RemoveIfExist(outfname) infile = open(fname, 'r') outfile = open(outfname, 'w') ExportList=[] FirstAreaFound=False for line in infile: #print ("checking %s" % line) if(not FirstAreaFound): m = gAreaPattern.search(line) if(m): #print "matched AREA" FirstAreaFound=True outfile.write (" INCLUDE AsmMacroExport.inc\n") continue m = gExportPattern.search(line) if(m): #print "matched EXPORT" #print "group 0 is %s" % m.group(0) #print "group 1 is %s" % m.group(1) ExportList.append(m.group(1)) continue m = gLabelPattern.search(line) if(m): #print "matched label" #print "group 0 is %s" % m.group(0) label=m.group(0) if ( label in ExportList ): #print "found exported label" outfile.write (" RVCT_ASM_EXPORT %s\n" % label) continue outfile.write(line) outfile.close(); infile.close() oldname = fname + '.bak' RemoveIfExist(oldname) os.rename(fname, oldname) os.rename(outfname, fname) os.remove(oldname) return def RemoveIfExist(fname): try: os.remove(fname) except: pass return if __name__ == "__main__": #print "call with args: %s" % sys.argv[1] #files = glob.glob(sys.argv[1]) #print "files is %s" % files #ProcessFiles(files) ProcessFiles(sys.argv[1:]) -----Original Message----- From: edk2-devel [mailto:[email protected]] On Behalf Of Cohen, Eugene Sent: Wednesday, November 25, 2015 12:11 PM To: [email protected] Subject: [edk2] [PATCH 3/3] ArmPkg: update RVCT assembly functions to use new RVCT_ASM_EXPORT macro This has the effect of splitting assembly functions into their own sections so the linker can remove unused ones to save space. This has been tested to build with ArmPkg.dsc with RVCT 4. The majority of the conversion was performed with the attached python script. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <[email protected]> --- .../ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Helper.asm | 5 +- ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.asm | 26 ++--- ArmPkg/Drivers/CpuDxe/ArmV4/ExceptionSupport.asm | 14 +-- ArmPkg/Drivers/CpuDxe/ArmV6/ExceptionSupport.asm | 14 +-- ArmPkg/Library/ArmHvcLib/Arm/ArmHvc.asm | 5 +- ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm | 46 +++------ .../Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.asm | 64 +++++------- ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm | 109 +++++++-------------- ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm | 84 ++++++---------- ArmPkg/Library/ArmSmcLib/Arm/ArmSmc.asm | 5 +- ArmPkg/Library/ArmSmcLibNull/Arm/ArmSmcNull.asm | 5 +- ArmPkg/Library/BaseMemoryLibStm/Arm/CopyMem.asm | 5 +- ArmPkg/Library/BaseMemoryLibStm/Arm/SetMem.asm | 5 +- .../Library/BaseMemoryLibStm/BaseMemoryLibStm.inf | 1 + ArmPkg/Library/BaseMemoryLibVstm/Arm/CopyMem.asm | 5 +- ArmPkg/Library/BaseMemoryLibVstm/Arm/SetMem.asm | 5 +- .../BaseMemoryLibVstm/BaseMemoryLibVstm.inf | 1 + ArmPkg/Library/CompilerIntrinsicsLib/Arm/div.asm | 14 +-- ArmPkg/Library/CompilerIntrinsicsLib/Arm/lasr.asm | 5 +- .../Library/CompilerIntrinsicsLib/Arm/ldivmod.asm | 5 +- ArmPkg/Library/CompilerIntrinsicsLib/Arm/llsl.asm | 5 +- ArmPkg/Library/CompilerIntrinsicsLib/Arm/llsr.asm | 5 +- .../Library/CompilerIntrinsicsLib/Arm/memcpy.asm | 5 +- .../Library/CompilerIntrinsicsLib/Arm/memcpy4.asm | 5 +- .../Library/CompilerIntrinsicsLib/Arm/memmove.asm | 5 +- .../Library/CompilerIntrinsicsLib/Arm/memset.asm | 11 +-- ArmPkg/Library/CompilerIntrinsicsLib/Arm/mullu.asm | 8 +- .../Library/CompilerIntrinsicsLib/Arm/switch.asm | 5 +- ArmPkg/Library/CompilerIntrinsicsLib/Arm/uldiv.asm | 5 +- ArmPkg/Library/CompilerIntrinsicsLib/Arm/uread.asm | 8 +- .../Library/CompilerIntrinsicsLib/Arm/uwrite.asm | 8 +- .../CompilerIntrinsicsLib.inf | 1 + 32 files changed, 178 insertions(+), 316 deletions(-) diff --git a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Helper.asm b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Helper.asm index 7150834..1417c9a 100644 --- a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Helper.asm +++ b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Helper.asm @@ -15,16 +15,15 @@ #include <Library/ArmCpuLib.h> #include <Chipset/ArmCortexA9.h> + INCLUDE AsmMacroExport.inc INCLUDE AsmMacroIoLib.inc - EXPORT ArmGetScuBaseAddress PRESERVE8 - AREA ArmCortexA9Helper, CODE, READONLY // IN None // OUT r0 = SCU Base Address -ArmGetScuBaseAddress + RVCT_ASM_EXPORT ArmGetScuBaseAddress // Read Configuration Base Address Register. ArmCBar cannot be called to get // the Configuration BAR as a stack is not necessary setup. The SCU is at the // offset 0x0000 from the Private Memory Region. diff --git a/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.asm b/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.asm index 92c3236..4228fb5 100644 --- a/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.asm +++ b/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.asm @@ -13,23 +13,15 @@ // For the moment we assume this will run in SVC mode on ARMv7 - EXPORT ArmGicV3GetControlSystemRegisterEnable - EXPORT ArmGicV3SetControlSystemRegisterEnable - EXPORT ArmGicV3EnableInterruptInterface - EXPORT ArmGicV3DisableInterruptInterface - EXPORT ArmGicV3EndOfInterrupt - EXPORT ArmGicV3AcknowledgeInterrupt - EXPORT ArmGicV3SetPriorityMask - EXPORT ArmGicV3SetBinaryPointer - AREA ArmGicV3, CODE, READONLY + INCLUDE AsmMacroExport.inc //UINT32 //EFIAPI //ArmGicGetControlSystemRegisterEnable ( // VOID // ); -ArmGicV3GetControlSystemRegisterEnable + RVCT_ASM_EXPORT ArmGicV3GetControlSystemRegisterEnable mrc p15, 0, r0, c12, c12, 5 // ICC_SRE bx lr @@ -38,7 +30,7 @@ ArmGicV3GetControlSystemRegisterEnable //ArmGicSetControlSystemRegisterEnable ( // IN UINT32 ControlSystemRegisterEnable // ); -ArmGicV3SetControlSystemRegisterEnable + RVCT_ASM_EXPORT ArmGicV3SetControlSystemRegisterEnable mcr p15, 0, r0, c12, c12, 5 // ICC_SRE isb bx lr @@ -47,7 +39,7 @@ ArmGicV3SetControlSystemRegisterEnable //ArmGicV3EnableInterruptInterface ( // VOID // ); -ArmGicV3EnableInterruptInterface + RVCT_ASM_EXPORT ArmGicV3EnableInterruptInterface mov r0, #1 mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1 bx lr @@ -56,7 +48,7 @@ ArmGicV3EnableInterruptInterface //ArmGicV3DisableInterruptInterface ( // VOID // ); -ArmGicV3DisableInterruptInterface + RVCT_ASM_EXPORT ArmGicV3DisableInterruptInterface mov r0, #0 mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1 bx lr @@ -65,7 +57,7 @@ ArmGicV3DisableInterruptInterface //ArmGicV3EndOfInterrupt ( // IN UINTN InterruptId // ); -ArmGicV3EndOfInterrupt + RVCT_ASM_EXPORT ArmGicV3EndOfInterrupt mcr p15, 0, r0, c12, c12, 1 //ICC_EOIR1 bx lr @@ -73,7 +65,7 @@ ArmGicV3EndOfInterrupt //ArmGicV3AcknowledgeInterrupt ( // VOID // ); -ArmGicV3AcknowledgeInterrupt + RVCT_ASM_EXPORT ArmGicV3AcknowledgeInterrupt mrc p15, 0, r0, c12, c8, 0 //ICC_IAR1 bx lr @@ -81,7 +73,7 @@ ArmGicV3AcknowledgeInterrupt //ArmGicV3SetPriorityMask ( // IN UINTN Priority // ); -ArmGicV3SetPriorityMask + RVCT_ASM_EXPORT ArmGicV3SetPriorityMask mcr p15, 0, r0, c4, c6, 0 //ICC_PMR bx lr @@ -89,7 +81,7 @@ ArmGicV3SetPriorityMask //ArmGicV3SetBinaryPointer ( // IN UINTN BinaryPoint // ); -ArmGicV3SetBinaryPointer + RVCT_ASM_EXPORT ArmGicV3SetBinaryPointer mcr p15, 0, r0, c12, c12, 3 //ICC_BPR1 bx lr diff --git a/ArmPkg/Drivers/CpuDxe/ArmV4/ExceptionSupport.asm b/ArmPkg/Drivers/CpuDxe/ArmV4/ExceptionSupport.asm index 9f09a0b..c086993 100644 --- a/ArmPkg/Drivers/CpuDxe/ArmV4/ExceptionSupport.asm +++ b/ArmPkg/Drivers/CpuDxe/ArmV4/ExceptionSupport.asm @@ -12,16 +12,12 @@ // //------------------------------------------------------------------------------ - EXPORT ExceptionHandlersStart - EXPORT ExceptionHandlersEnd - EXPORT CommonExceptionEntry - EXPORT AsmCommonExceptionEntry + INCLUDE AsmMacroExport.inc IMPORT CommonCExceptionHandler PRESERVE8 - AREA DxeExceptionHandlers, CODE, READONLY -ExceptionHandlersStart + RVCT_ASM_EXPORT ExceptionHandlersStart Reset b ResetEntry @@ -99,12 +95,12 @@ FiqEntry ldr R1,CommonExceptionEntry bx R1 -CommonExceptionEntry + RVCT_ASM_EXPORT CommonExceptionEntry dcd 0x12345678 -ExceptionHandlersEnd + RVCT_ASM_EXPORT ExceptionHandlersEnd -AsmCommonExceptionEntry + RVCT_ASM_EXPORT AsmCommonExceptionEntry mrc p15, 0, r1, c6, c0, 2 ; Read IFAR stmfd SP!,{R1} ; Store the IFAR diff --git a/ArmPkg/Drivers/CpuDxe/ArmV6/ExceptionSupport.asm b/ArmPkg/Drivers/CpuDxe/ArmV6/ExceptionSupport.asm index b28ff9f..293e0a0 100644 --- a/ArmPkg/Drivers/CpuDxe/ArmV6/ExceptionSupport.asm +++ b/ArmPkg/Drivers/CpuDxe/ArmV6/ExceptionSupport.asm @@ -53,20 +53,16 @@ This is the stack constructed by the exception handler (low address to high addr */ - EXPORT ExceptionHandlersStart - EXPORT ExceptionHandlersEnd - EXPORT CommonExceptionEntry - EXPORT AsmCommonExceptionEntry + INCLUDE AsmMacroExport.inc IMPORT CommonCExceptionHandler PRESERVE8 - AREA DxeExceptionHandlers, CODE, READONLY, CODEALIGN, ALIGN=5 // // This code gets copied to the ARM vector table // ExceptionHandlersStart - ExceptionHandlersEnd gets copied // -ExceptionHandlersStart + RVCT_ASM_EXPORT ExceptionHandlersStart Reset b ResetEntry @@ -189,16 +185,16 @@ FiqEntry // // This gets patched by the C code that patches in the vector table // -CommonExceptionEntry + RVCT_ASM_EXPORT CommonExceptionEntry dcd AsmCommonExceptionEntry -ExceptionHandlersEnd + RVCT_ASM_EXPORT ExceptionHandlersEnd // // This code runs from CpuDxe driver loaded address. It is patched into // CommonExceptionEntry. // -AsmCommonExceptionEntry + RVCT_ASM_EXPORT AsmCommonExceptionEntry mrc p15, 0, R1, c6, c0, 2 ; Read IFAR str R1, [SP, #0x50] ; Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR diff --git a/ArmPkg/Library/ArmHvcLib/Arm/ArmHvc.asm b/ArmPkg/Library/ArmHvcLib/Arm/ArmHvc.asm index bac26fb..fe4b174 100644 --- a/ArmPkg/Library/ArmHvcLib/Arm/ArmHvc.asm +++ b/ArmPkg/Library/ArmHvcLib/Arm/ArmHvc.asm @@ -12,11 +12,10 @@ // // - EXPORT ArmCallHvc - AREA ArmHvc, CODE, READONLY + INCLUDE AsmMacroExport.inc -ArmCallHvc + RVCT_ASM_EXPORT ArmCallHvc push {r4-r8} // r0 will be popped just after the HVC call push {r0} diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm index 8179232..cbbe8db 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm @@ -14,27 +14,13 @@ //------------------------------------------------------------------------------ - EXPORT ArmIsMpCore - EXPORT ArmHasMpExtensions - EXPORT ArmEnableAsynchronousAbort - EXPORT ArmDisableAsynchronousAbort - EXPORT ArmEnableIrq - EXPORT ArmDisableIrq - EXPORT ArmEnableFiq - EXPORT ArmDisableFiq - EXPORT ArmEnableInterrupts - EXPORT ArmDisableInterrupts - EXPORT ReadCCSIDR - EXPORT ReadCLIDR - EXPORT ArmReadNsacr - EXPORT ArmWriteNsacr - - AREA ArmLibSupportV7, CODE, READONLY + + INCLUDE AsmMacroExport.inc //------------------------------------------------------------------------------ -ArmIsMpCore + RVCT_ASM_EXPORT ArmIsMpCore mrc p15,0,R0,c0,c0,5 // Get Multiprocessing extension (bit31) & U bit (bit30) and R0, R0, #0xC0000000 @@ -44,48 +30,48 @@ ArmIsMpCore movne R0, #0 bx LR -ArmHasMpExtensions + RVCT_ASM_EXPORT ArmHasMpExtensions mrc p15,0,R0,c0,c0,5 // Get Multiprocessing extension (bit31) lsr R0, R0, #31 bx LR -ArmEnableAsynchronousAbort + RVCT_ASM_EXPORT ArmEnableAsynchronousAbort cpsie a isb bx LR -ArmDisableAsynchronousAbort + RVCT_ASM_EXPORT ArmDisableAsynchronousAbort cpsid a isb bx LR -ArmEnableIrq + RVCT_ASM_EXPORT ArmEnableIrq cpsie i isb bx LR -ArmDisableIrq + RVCT_ASM_EXPORT ArmDisableIrq cpsid i isb bx LR -ArmEnableFiq + RVCT_ASM_EXPORT ArmEnableFiq cpsie f isb bx LR -ArmDisableFiq + RVCT_ASM_EXPORT ArmDisableFiq cpsid f isb bx LR -ArmEnableInterrupts + RVCT_ASM_EXPORT ArmEnableInterrupts cpsie if isb bx LR -ArmDisableInterrupts + RVCT_ASM_EXPORT ArmDisableInterrupts cpsid if isb bx LR @@ -94,7 +80,7 @@ ArmDisableInterrupts // ReadCCSIDR ( // IN UINT32 CSSELR // ) -ReadCCSIDR + RVCT_ASM_EXPORT ReadCCSIDR mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR) isb mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR) @@ -104,15 +90,15 @@ ReadCCSIDR // ReadCLIDR ( // IN UINT32 CSSELR // ) -ReadCLIDR + RVCT_ASM_EXPORT ReadCLIDR mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register bx lr -ArmReadNsacr + RVCT_ASM_EXPORT ArmReadNsacr mrc p15, 0, r0, c1, c1, 2 bx lr -ArmWriteNsacr + RVCT_ASM_EXPORT ArmWriteNsacr mcr p15, 0, r0, c1, c1, 2 bx lr diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.asm index 514830d..a53dd60 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.asm +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.asm @@ -12,107 +12,87 @@ // //------------------------------------------------------------------------------ - EXPORT ArmReadCntFrq - EXPORT ArmWriteCntFrq - EXPORT ArmReadCntPct - EXPORT ArmReadCntkCtl - EXPORT ArmWriteCntkCtl - EXPORT ArmReadCntpTval - EXPORT ArmWriteCntpTval - EXPORT ArmReadCntpCtl - EXPORT ArmWriteCntpCtl - EXPORT ArmReadCntvTval - EXPORT ArmWriteCntvTval - EXPORT ArmReadCntvCtl - EXPORT ArmWriteCntvCtl - EXPORT ArmReadCntvCt - EXPORT ArmReadCntpCval - EXPORT ArmWriteCntpCval - EXPORT ArmReadCntvCval - EXPORT ArmWriteCntvCval - EXPORT ArmReadCntvOff - EXPORT ArmWriteCntvOff - - AREA ArmV7ArchTimerSupport, CODE, READONLY + + INCLUDE AsmMacroExport.inc PRESERVE8 -ArmReadCntFrq + RVCT_ASM_EXPORT ArmReadCntFrq mrc p15, 0, r0, c14, c0, 0 ; Read CNTFRQ bx lr -ArmWriteCntFrq + RVCT_ASM_EXPORT ArmWriteCntFrq mcr p15, 0, r0, c14, c0, 0 ; Write to CNTFRQ bx lr -ArmReadCntPct + RVCT_ASM_EXPORT ArmReadCntPct mrrc p15, 0, r0, r1, c14 ; Read CNTPT (Physical counter register) bx lr -ArmReadCntkCtl + RVCT_ASM_EXPORT ArmReadCntkCtl mrc p15, 0, r0, c14, c1, 0 ; Read CNTK_CTL (Timer PL1 Control Register) bx lr -ArmWriteCntkCtl + RVCT_ASM_EXPORT ArmWriteCntkCtl mcr p15, 0, r0, c14, c1, 0 ; Write to CNTK_CTL (Timer PL1 Control Register) bx lr -ArmReadCntpTval + RVCT_ASM_EXPORT ArmReadCntpTval mrc p15, 0, r0, c14, c2, 0 ; Read CNTP_TVAL (PL1 physical timer value register) bx lr -ArmWriteCntpTval + RVCT_ASM_EXPORT ArmWriteCntpTval mcr p15, 0, r0, c14, c2, 0 ; Write to CNTP_TVAL (PL1 physical timer value register) bx lr -ArmReadCntpCtl + RVCT_ASM_EXPORT ArmReadCntpCtl mrc p15, 0, r0, c14, c2, 1 ; Read CNTP_CTL (PL1 Physical Timer Control Register) bx lr -ArmWriteCntpCtl + RVCT_ASM_EXPORT ArmWriteCntpCtl mcr p15, 0, r0, c14, c2, 1 ; Write to CNTP_CTL (PL1 Physical Timer Control Register) bx lr -ArmReadCntvTval + RVCT_ASM_EXPORT ArmReadCntvTval mrc p15, 0, r0, c14, c3, 0 ; Read CNTV_TVAL (Virtual Timer Value register) bx lr -ArmWriteCntvTval + RVCT_ASM_EXPORT ArmWriteCntvTval mcr p15, 0, r0, c14, c3, 0 ; Write to CNTV_TVAL (Virtual Timer Value register) bx lr -ArmReadCntvCtl + RVCT_ASM_EXPORT ArmReadCntvCtl mrc p15, 0, r0, c14, c3, 1 ; Read CNTV_CTL (Virtual Timer Control Register) bx lr -ArmWriteCntvCtl + RVCT_ASM_EXPORT ArmWriteCntvCtl mcr p15, 0, r0, c14, c3, 1 ; Write to CNTV_CTL (Virtual Timer Control Register) bx lr -ArmReadCntvCt + RVCT_ASM_EXPORT ArmReadCntvCt mrrc p15, 1, r0, r1, c14 ; Read CNTVCT (Virtual Count Register) bx lr -ArmReadCntpCval + RVCT_ASM_EXPORT ArmReadCntpCval mrrc p15, 2, r0, r1, c14 ; Read CNTP_CTVAL (Physical Timer Compare Value Register) bx lr -ArmWriteCntpCval + RVCT_ASM_EXPORT ArmWriteCntpCval mcrr p15, 2, r0, r1, c14 ; Write to CNTP_CTVAL (Physical Timer Compare Value Register) bx lr -ArmReadCntvCval + RVCT_ASM_EXPORT ArmReadCntvCval mrrc p15, 3, r0, r1, c14 ; Read CNTV_CTVAL (Virtual Timer Compare Value Register) bx lr -ArmWriteCntvCval + RVCT_ASM_EXPORT ArmWriteCntvCval mcrr p15, 3, r0, r1, c14 ; write to CNTV_CTVAL (Virtual Timer Compare Value Register) bx lr -ArmReadCntvOff + RVCT_ASM_EXPORT ArmReadCntvOff mrrc p15, 4, r0, r1, c14 ; Read CNTVOFF (virtual Offset register) bx lr -ArmWriteCntvOff + RVCT_ASM_EXPORT ArmWriteCntvOff mcrr p15, 4, r0, r1, c14 ; Write to CNTVOFF (Virtual Offset register) bx lr diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm index 542157b..df7e22d 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm @@ -13,43 +13,8 @@ // //------------------------------------------------------------------------------ - EXPORT ArmInvalidateInstructionCache - EXPORT ArmInvalidateDataCacheEntryByMVA - EXPORT ArmCleanDataCacheEntryByMVA - EXPORT ArmCleanInvalidateDataCacheEntryByMVA - EXPORT ArmInvalidateDataCacheEntryBySetWay - EXPORT ArmCleanDataCacheEntryBySetWay - EXPORT ArmCleanInvalidateDataCacheEntryBySetWay - EXPORT ArmEnableMmu - EXPORT ArmDisableMmu - EXPORT ArmDisableCachesAndMmu - EXPORT ArmMmuEnabled - EXPORT ArmEnableDataCache - EXPORT ArmDisableDataCache - EXPORT ArmEnableInstructionCache - EXPORT ArmDisableInstructionCache - EXPORT ArmEnableSWPInstruction - EXPORT ArmEnableBranchPrediction - EXPORT ArmDisableBranchPrediction - EXPORT ArmSetLowVectors - EXPORT ArmSetHighVectors - EXPORT ArmV7AllDataCachesOperation - EXPORT ArmDataMemoryBarrier - EXPORT ArmDataSynchronizationBarrier - EXPORT ArmInstructionSynchronizationBarrier - EXPORT ArmReadVBar - EXPORT ArmWriteVBar - EXPORT ArmEnableVFP - EXPORT ArmCallWFI - EXPORT ArmReadCbar - EXPORT ArmReadMpidr - EXPORT ArmReadTpidrurw - EXPORT ArmWriteTpidrurw - EXPORT ArmIsArchTimerImplemented - EXPORT ArmReadIdPfr1 - EXPORT ArmReadIdMmfr0 - - AREA ArmV7Support, CODE, READONLY + + INCLUDE AsmMacroExport.inc PRESERVE8 DC_ON EQU ( 0x1:SHL:2 ) @@ -60,41 +25,41 @@ CTRL_B_BIT EQU (1 << 7) CTRL_I_BIT EQU (1 << 12) -ArmInvalidateDataCacheEntryByMVA + RVCT_ASM_EXPORT ArmInvalidateDataCacheEntryByMVA mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line bx lr -ArmCleanDataCacheEntryByMVA + RVCT_ASM_EXPORT ArmCleanDataCacheEntryByMVA mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line bx lr -ArmCleanInvalidateDataCacheEntryByMVA + RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryByMVA mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line bx lr -ArmInvalidateDataCacheEntryBySetWay + RVCT_ASM_EXPORT ArmInvalidateDataCacheEntryBySetWay mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line bx lr -ArmCleanInvalidateDataCacheEntryBySetWay + RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryBySetWay mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line bx lr -ArmCleanDataCacheEntryBySetWay + RVCT_ASM_EXPORT ArmCleanDataCacheEntryBySetWay mcr p15, 0, r0, c7, c10, 2 ; Clean this line bx lr -ArmInvalidateInstructionCache + RVCT_ASM_EXPORT ArmInvalidateInstructionCache mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache isb bx LR -ArmEnableMmu + RVCT_ASM_EXPORT ArmEnableMmu mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data) @@ -102,7 +67,7 @@ ArmEnableMmu isb bx LR -ArmDisableMmu + RVCT_ASM_EXPORT ArmDisableMmu mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data) @@ -113,7 +78,7 @@ ArmDisableMmu isb bx LR -ArmDisableCachesAndMmu + RVCT_ASM_EXPORT ArmDisableCachesAndMmu mrc p15, 0, r0, c1, c0, 0 ; Get control register bic r0, r0, #CTRL_M_BIT ; Disable MMU bic r0, r0, #CTRL_C_BIT ; Disable D Cache @@ -123,12 +88,12 @@ ArmDisableCachesAndMmu isb bx LR -ArmMmuEnabled + RVCT_ASM_EXPORT ArmMmuEnabled mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) and R0,R0,#1 bx LR -ArmEnableDataCache + RVCT_ASM_EXPORT ArmEnableDataCache ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) orr R0,R0,R1 ; Set SCTLR.C bit : Data and unified caches enabled @@ -137,7 +102,7 @@ ArmEnableDataCache isb bx LR -ArmDisableDataCache + RVCT_ASM_EXPORT ArmDisableDataCache ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified caches disabled @@ -146,7 +111,7 @@ ArmDisableDataCache isb bx LR -ArmEnableInstructionCache + RVCT_ASM_EXPORT ArmEnableInstructionCache ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) orr R0,R0,R1 ; Set SCTLR.I bit : Instruction caches enabled @@ -155,7 +120,7 @@ ArmEnableInstructionCache isb bx LR -ArmDisableInstructionCache + RVCT_ASM_EXPORT ArmDisableInstructionCache ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) BIC R0,R0,R1 ; Clear SCTLR.I bit : Instruction caches disabled @@ -163,14 +128,14 @@ ArmDisableInstructionCache isb bx LR -ArmEnableSWPInstruction + RVCT_ASM_EXPORT ArmEnableSWPInstruction mrc p15, 0, r0, c1, c0, 0 orr r0, r0, #0x00000400 mcr p15, 0, r0, c1, c0, 0 isb bx LR -ArmEnableBranchPrediction + RVCT_ASM_EXPORT ArmEnableBranchPrediction mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data) orr r0, r0, #0x00000800 ; mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data) @@ -178,7 +143,7 @@ ArmEnableBranchPrediction isb bx LR -ArmDisableBranchPrediction + RVCT_ASM_EXPORT ArmDisableBranchPrediction mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data) bic r0, r0, #0x00000800 ; mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data) @@ -186,21 +151,21 @@ ArmDisableBranchPrediction isb bx LR -ArmSetLowVectors + RVCT_ASM_EXPORT ArmSetLowVectors mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data) bic r0, r0, #0x00002000 ; clear V bit mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data) isb bx LR -ArmSetHighVectors + RVCT_ASM_EXPORT ArmSetHighVectors mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data) orr r0, r0, #0x00002000 ; Set V bit mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data) isb bx LR -ArmV7AllDataCachesOperation + RVCT_ASM_EXPORT ArmV7AllDataCachesOperation stmfd SP!,{r4-r12, LR} mov R1, R0 ; Save Function call in R1 mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR @@ -249,24 +214,24 @@ Finished ldmfd SP!, {r4-r12, lr} bx LR -ArmDataMemoryBarrier + RVCT_ASM_EXPORT ArmDataMemoryBarrier dmb bx LR -ArmDataSynchronizationBarrier + RVCT_ASM_EXPORT ArmDataSynchronizationBarrier dsb bx LR -ArmInstructionSynchronizationBarrier + RVCT_ASM_EXPORT ArmInstructionSynchronizationBarrier isb bx LR -ArmReadVBar + RVCT_ASM_EXPORT ArmReadVBar // Set the Address of the Vector Table in the VBAR register mrc p15, 0, r0, c12, c0, 0 bx lr -ArmWriteVBar + RVCT_ASM_EXPORT ArmWriteVBar // Set the Address of the Vector Table in the VBAR register mcr p15, 0, r0, c12, c0, 0 // Ensure the SCTLR.V bit is clear @@ -276,7 +241,7 @@ ArmWriteVBar isb bx lr -ArmEnableVFP + RVCT_ASM_EXPORT ArmEnableVFP // Read CPACR (Coprocessor Access Control Register) mrc p15, 0, r0, c1, c0, 2 // Enable VPF access (Full Access to CP10, CP11) (V* instructions) @@ -289,37 +254,37 @@ ArmEnableVFP mcr p10,#0x7,r0,c8,c0,#0 bx lr -ArmCallWFI + RVCT_ASM_EXPORT ArmCallWFI wfi bx lr //Note: Return 0 in Uniprocessor implementation -ArmReadCbar + RVCT_ASM_EXPORT ArmReadCbar mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register bx lr -ArmReadMpidr + RVCT_ASM_EXPORT ArmReadMpidr mrc p15, 0, r0, c0, c0, 5 ; read MPIDR bx lr -ArmReadTpidrurw + RVCT_ASM_EXPORT ArmReadTpidrurw mrc p15, 0, r0, c13, c0, 2 ; read TPIDRURW bx lr -ArmWriteTpidrurw + RVCT_ASM_EXPORT ArmWriteTpidrurw mcr p15, 0, r0, c13, c0, 2 ; write TPIDRURW bx lr -ArmIsArchTimerImplemented + RVCT_ASM_EXPORT ArmIsArchTimerImplemented mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1 and r0, r0, #0x000F0000 bx lr -ArmReadIdPfr1 + RVCT_ASM_EXPORT ArmReadIdPfr1 mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1 Register bx lr -ArmReadIdMmfr0 + RVCT_ASM_EXPORT ArmReadIdMmfr0 mrc p15, 0, r0, c0, c1, 4 ; Read ID_MMFR0 Register bx lr diff --git a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm index 0974d46..bdd862a 100644 --- a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm +++ b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm @@ -17,62 +17,36 @@ INCLUDE AsmMacroIoLib.inc - EXPORT ArmReadMidr - EXPORT ArmCacheInfo - EXPORT ArmGetInterruptState - EXPORT ArmGetFiqState - EXPORT ArmGetTTBR0BaseAddress - EXPORT ArmSetTTBR0 - EXPORT ArmSetDomainAccessControl - EXPORT CPSRMaskInsert - EXPORT CPSRRead - EXPORT ArmReadCpacr - EXPORT ArmWriteCpacr - EXPORT ArmWriteAuxCr - EXPORT ArmReadAuxCr - EXPORT ArmInvalidateTlb - EXPORT ArmUpdateTranslationTableEntry - EXPORT ArmReadScr - EXPORT ArmWriteScr - EXPORT ArmReadMVBar - EXPORT ArmWriteMVBar - EXPORT ArmReadHVBar - EXPORT ArmWriteHVBar - EXPORT ArmCallWFE - EXPORT ArmCallSEV - EXPORT ArmReadSctlr - EXPORT ArmReadCpuActlr - EXPORT ArmWriteCpuActlr - - AREA ArmLibSupport, CODE, READONLY - -ArmReadMidr + + INCLUDE AsmMacroExport.inc + + RVCT_ASM_EXPORT ArmReadMidr mrc p15,0,R0,c0,c0,0 bx LR -ArmCacheInfo + RVCT_ASM_EXPORT ArmCacheInfo mrc p15,0,R0,c0,c0,1 bx LR -ArmGetInterruptState + RVCT_ASM_EXPORT ArmGetInterruptState mrs R0,CPSR tst R0,#0x80 // Check if IRQ is enabled. moveq R0,#1 movne R0,#0 bx LR -ArmGetFiqState + RVCT_ASM_EXPORT ArmGetFiqState mrs R0,CPSR tst R0,#0x40 // Check if FIQ is enabled. moveq R0,#1 movne R0,#0 bx LR -ArmSetDomainAccessControl + RVCT_ASM_EXPORT ArmSetDomainAccessControl mcr p15,0,r0,c3,c0,0 bx lr -CPSRMaskInsert // on entry, r0 is the mask and r1 is the field to insert + RVCT_ASM_EXPORT CPSRMaskInsert stmfd sp!, {r4-r12, lr} // save all the banked registers mov r3, sp // copy the stack pointer into a non-banked register mrs r2, cpsr // read the cpsr @@ -85,33 +59,33 @@ CPSRMaskInsert // on entry, r0 is the mask and r1 is the field to insert ldmfd sp!, {r4-r12, lr} // restore registers bx lr // return (hopefully thumb-safe!) // return (hopefully thumb-safe!) -CPSRRead + RVCT_ASM_EXPORT CPSRRead mrs r0, cpsr bx lr -ArmReadCpacr + RVCT_ASM_EXPORT ArmReadCpacr mrc p15, 0, r0, c1, c0, 2 bx lr -ArmWriteCpacr + RVCT_ASM_EXPORT ArmWriteCpacr mcr p15, 0, r0, c1, c0, 2 isb bx lr -ArmWriteAuxCr + RVCT_ASM_EXPORT ArmWriteAuxCr mcr p15, 0, r0, c1, c0, 1 bx lr -ArmReadAuxCr + RVCT_ASM_EXPORT ArmReadAuxCr mrc p15, 0, r0, c1, c0, 1 bx lr -ArmSetTTBR0 + RVCT_ASM_EXPORT ArmSetTTBR0 mcr p15,0,r0,c2,c0,0 isb bx lr -ArmGetTTBR0BaseAddress + RVCT_ASM_EXPORT ArmGetTTBR0BaseAddress mrc p15,0,r0,c2,c0,0 LoadConstantToReg(0xFFFFC000, r1) and r0, r0, r1 @@ -124,7 +98,7 @@ ArmGetTTBR0BaseAddress // IN VOID *TranslationTableEntry // R0 // IN VOID *MVA // R1 // ); -ArmUpdateTranslationTableEntry + RVCT_ASM_EXPORT ArmUpdateTranslationTableEntry mcr p15,0,R0,c7,c14,1 // DCCIMVAC Clean data cache by MVA dsb mcr p15,0,R1,c8,c7,1 // TLBIMVA TLB Invalidate MVA @@ -133,7 +107,7 @@ ArmUpdateTranslationTableEntry isb bx lr -ArmInvalidateTlb + RVCT_ASM_EXPORT ArmInvalidateTlb mov r0,#0 mcr p15,0,r0,c8,c7,0 mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp @@ -141,48 +115,48 @@ ArmInvalidateTlb isb bx lr -ArmReadScr + RVCT_ASM_EXPORT ArmReadScr mrc p15, 0, r0, c1, c1, 0 bx lr -ArmWriteScr + RVCT_ASM_EXPORT ArmWriteScr mcr p15, 0, r0, c1, c1, 0 bx lr -ArmReadHVBar + RVCT_ASM_EXPORT ArmReadHVBar mrc p15, 4, r0, c12, c0, 0 bx lr -ArmWriteHVBar + RVCT_ASM_EXPORT ArmWriteHVBar mcr p15, 4, r0, c12, c0, 0 bx lr -ArmReadMVBar + RVCT_ASM_EXPORT ArmReadMVBar mrc p15, 0, r0, c12, c0, 1 bx lr -ArmWriteMVBar + RVCT_ASM_EXPORT ArmWriteMVBar mcr p15, 0, r0, c12, c0, 1 bx lr -ArmCallWFE + RVCT_ASM_EXPORT ArmCallWFE wfe bx lr -ArmCallSEV + RVCT_ASM_EXPORT ArmCallSEV sev bx lr -ArmReadSctlr + RVCT_ASM_EXPORT ArmReadSctlr mrc p15, 0, r0, c1, c0, 0 // Read SCTLR into R0 (Read control register configuration data) bx lr -ArmReadCpuActlr + RVCT_ASM_EXPORT ArmReadCpuActlr mrc p15, 0, r0, c1, c0, 1 bx lr -ArmWriteCpuActlr + RVCT_ASM_EXPORT ArmWriteCpuActlr mcr p15, 0, r0, c1, c0, 1 dsb isb diff --git a/ArmPkg/Library/ArmSmcLib/Arm/ArmSmc.asm b/ArmPkg/Library/ArmSmcLib/Arm/ArmSmc.asm index 50580f7..b82cf39 100644 --- a/ArmPkg/Library/ArmSmcLib/Arm/ArmSmc.asm +++ b/ArmPkg/Library/ArmSmcLib/Arm/ArmSmc.asm @@ -11,11 +11,10 @@ // // - EXPORT ArmCallSmc - AREA ArmSmc, CODE, READONLY + INCLUDE AsmMacroExport.inc -ArmCallSmc + RVCT_ASM_EXPORT ArmCallSmc push {r4-r8} // r0 will be popped just after the SMC call push {r0} diff --git a/ArmPkg/Library/ArmSmcLibNull/Arm/ArmSmcNull.asm b/ArmPkg/Library/ArmSmcLibNull/Arm/ArmSmcNull.asm index 3d3f554..3dcb25f 100644 --- a/ArmPkg/Library/ArmSmcLibNull/Arm/ArmSmcNull.asm +++ b/ArmPkg/Library/ArmSmcLibNull/Arm/ArmSmcNull.asm @@ -11,11 +11,10 @@ // // - EXPORT ArmCallSmc - AREA ArmSmc, CODE, READONLY + INCLUDE AsmMacroExport.inc -ArmCallSmc + RVCT_ASM_EXPORT ArmCallSmc bx lr END diff --git a/ArmPkg/Library/BaseMemoryLibStm/Arm/CopyMem.asm b/ArmPkg/Library/BaseMemoryLibStm/Arm/CopyMem.asm index 0d22d75..686253e 100755 --- a/ArmPkg/Library/BaseMemoryLibStm/Arm/CopyMem.asm +++ b/ArmPkg/Library/BaseMemoryLibStm/Arm/CopyMem.asm @@ -37,11 +37,10 @@ InternalMemCopyMem ( IN UINTN Length ) **/ - EXPORT InternalMemCopyMem - AREA AsmMemStuff, CODE, READONLY + INCLUDE AsmMacroExport.inc -InternalMemCopyMem + RVCT_ASM_EXPORT InternalMemCopyMem stmfd sp!, {r4-r11, lr} // Save the input parameters in extra registers (r11 = destination, r14 = source, r12 = length) mov r11, r0 diff --git a/ArmPkg/Library/BaseMemoryLibStm/Arm/SetMem.asm b/ArmPkg/Library/BaseMemoryLibStm/Arm/SetMem.asm index a9f29e2..1d5191f 100755 --- a/ArmPkg/Library/BaseMemoryLibStm/Arm/SetMem.asm +++ b/ArmPkg/Library/BaseMemoryLibStm/Arm/SetMem.asm @@ -34,11 +34,10 @@ InternalMemSetMem ( ) **/ - EXPORT InternalMemSetMem - AREA AsmMemStuff, CODE, READONLY + INCLUDE AsmMacroExport.inc -InternalMemSetMem + RVCT_ASM_EXPORT InternalMemSetMem stmfd sp!, {r4-r11, lr} tst r0, #3 movne r3, #0 diff --git a/ArmPkg/Library/BaseMemoryLibStm/BaseMemoryLibStm.inf b/ArmPkg/Library/BaseMemoryLibStm/BaseMemoryLibStm.inf index c2f3e2f..eac6cef 100755 --- a/ArmPkg/Library/BaseMemoryLibStm/BaseMemoryLibStm.inf +++ b/ArmPkg/Library/BaseMemoryLibStm/BaseMemoryLibStm.inf @@ -61,6 +61,7 @@ [Packages] MdePkg/MdePkg.dec + ArmPkg/ArmPkg.dec [LibraryClasses] DebugLib diff --git a/ArmPkg/Library/BaseMemoryLibVstm/Arm/CopyMem.asm b/ArmPkg/Library/BaseMemoryLibVstm/Arm/CopyMem.asm index 17b79e5..5afd1e5 100755 --- a/ArmPkg/Library/BaseMemoryLibVstm/Arm/CopyMem.asm +++ b/ArmPkg/Library/BaseMemoryLibVstm/Arm/CopyMem.asm @@ -37,11 +37,10 @@ InternalMemCopyMem ( IN UINTN Length ) **/ - EXPORT InternalMemCopyMem - AREA AsmMemStuff, CODE, READONLY + INCLUDE AsmMacroExport.inc -InternalMemCopyMem + RVCT_ASM_EXPORT InternalMemCopyMem stmfd sp!, {r4, r9, lr} tst r0, #3 mov r4, r0 diff --git a/ArmPkg/Library/BaseMemoryLibVstm/Arm/SetMem.asm b/ArmPkg/Library/BaseMemoryLibVstm/Arm/SetMem.asm index 5226192..c4a7c2b 100755 --- a/ArmPkg/Library/BaseMemoryLibVstm/Arm/SetMem.asm +++ b/ArmPkg/Library/BaseMemoryLibVstm/Arm/SetMem.asm @@ -34,11 +34,10 @@ InternalMemSetMem ( ) **/ - EXPORT InternalMemSetMem - AREA AsmMemStuff, CODE, READONLY + INCLUDE AsmMacroExport.inc -InternalMemSetMem + RVCT_ASM_EXPORT InternalMemSetMem stmfd sp!, {lr} tst r0, #3 movne r3, #0 diff --git a/ArmPkg/Library/BaseMemoryLibVstm/BaseMemoryLibVstm.inf b/ArmPkg/Library/BaseMemoryLibVstm/BaseMemoryLibVstm.inf index eaff180..4c388fa 100755 --- a/ArmPkg/Library/BaseMemoryLibVstm/BaseMemoryLibVstm.inf +++ b/ArmPkg/Library/BaseMemoryLibVstm/BaseMemoryLibVstm.inf @@ -62,6 +62,7 @@ [Packages] MdePkg/MdePkg.dec + ArmPkg/ArmPkg.dec [LibraryClasses] DebugLib diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/div.asm b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/div.asm index b539e51..1855a47 100644 --- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/div.asm +++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/div.asm @@ -13,12 +13,8 @@ //------------------------------------------------------------------------------ - EXPORT __aeabi_uidiv - EXPORT __aeabi_uidivmod - EXPORT __aeabi_idiv - EXPORT __aeabi_idivmod - AREA Math, CODE, READONLY + INCLUDE AsmMacroExport.inc ; ;UINT32 @@ -29,8 +25,8 @@ ; ); ; -__aeabi_uidiv -__aeabi_uidivmod + RVCT_ASM_EXPORT __aeabi_uidiv + RVCT_ASM_EXPORT __aeabi_uidivmod RSBS r12, r1, r0, LSR #4 MOV r2, #0 BCC __arm_div4 @@ -47,8 +43,8 @@ __aeabi_uidivmod ; IN INT32 Divisor ; ); ; -__aeabi_idiv -__aeabi_idivmod + RVCT_ASM_EXPORT __aeabi_idiv + RVCT_ASM_EXPORT __aeabi_idivmod ORRS r12, r0, r1 BMI __arm_div_negative RSBS r12, r1, r0, LSR #1 diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/lasr.asm b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/lasr.asm index feb267a..35723ff 100644 --- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/lasr.asm +++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/lasr.asm @@ -13,9 +13,8 @@ //------------------------------------------------------------------------------ - EXPORT __aeabi_lasr - AREA Math, CODE, READONLY + INCLUDE AsmMacroExport.inc ; ;UINT32 @@ -25,7 +24,7 @@ ; IN UINT32 Divisor ; ); ; -__aeabi_lasr + RVCT_ASM_EXPORT __aeabi_lasr SUBS r3,r2,#0x20 BPL {pc} + 0x18 ; 0x1c RSB r3,r2,#0x20 diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ldivmod.asm b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ldivmod.asm index 9c14e89..c71bd59 100644 --- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ldivmod.asm +++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ldivmod.asm @@ -13,10 +13,9 @@ //------------------------------------------------------------------------------ - EXPORT __aeabi_ldivmod EXTERN __aeabi_uldivmod - AREA Math, CODE, READONLY + INCLUDE AsmMacroExport.inc ; ;UINT32 @@ -27,7 +26,7 @@ ; ); ; -__aeabi_ldivmod + RVCT_ASM_EXPORT __aeabi_ldivmod PUSH {r4,lr} ASRS r4,r1,#1 EOR r4,r4,r3,LSR #1 diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/llsl.asm b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/llsl.asm index f6fc208..a31e186 100644 --- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/llsl.asm +++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/llsl.asm @@ -13,9 +13,8 @@ //------------------------------------------------------------------------------ - EXPORT __aeabi_llsl - AREA Math, CODE, READONLY + INCLUDE AsmMacroExport.inc ; ;VOID @@ -27,7 +26,7 @@ ; ); ; -__aeabi_llsl + RVCT_ASM_EXPORT __aeabi_llsl SUBS r3,r2,#0x20 BPL {pc} + 0x18 ; 0x1c RSB r3,r2,#0x20 diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/llsr.asm b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/llsr.asm index 829c871..881db10 100644 --- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/llsr.asm +++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/llsr.asm @@ -13,9 +13,8 @@ //------------------------------------------------------------------------------ - EXPORT __aeabi_llsr - AREA Math, CODE, READONLY + INCLUDE AsmMacroExport.inc ; ;VOID @@ -26,7 +25,7 @@ ; IN UINT32 Size ; ); ; -__aeabi_llsr + RVCT_ASM_EXPORT __aeabi_llsr SUBS r3,r2,#0x20 BPL {pc} + 0x18 ; 0x1c RSB r3,r2,#0x20 diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memcpy.asm b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memcpy.asm index 60556b1..ae91197 100644 --- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memcpy.asm +++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memcpy.asm @@ -13,9 +13,8 @@ //------------------------------------------------------------------------------ - EXPORT __aeabi_memcpy - AREA Memcpy, CODE, READONLY + INCLUDE AsmMacroExport.inc ; ;VOID @@ -26,7 +25,7 @@ ; IN UINT32 Size ; ); ; -__aeabi_memcpy + RVCT_ASM_EXPORT __aeabi_memcpy cmp r2, #0 bxeq lr push {lr} diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memcpy4.asm b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memcpy4.asm index ecaa86f..3465e89 100644 --- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memcpy4.asm +++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memcpy4.asm @@ -13,9 +13,8 @@ //------------------------------------------------------------------------------ - EXPORT __aeabi_memcpy4 - AREA Memcpy4, CODE, READONLY + INCLUDE AsmMacroExport.inc ; ;VOID @@ -26,7 +25,7 @@ ; IN UINT32 Size ; ); ; -__aeabi_memcpy4 + RVCT_ASM_EXPORT __aeabi_memcpy4 stmdb sp!, {r4, lr} subs r2, r2, #32 ; 0x20 bcc memcpy4_label2 diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memmove.asm b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memmove.asm index 2147e29..09773b0 100755 --- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memmove.asm +++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memmove.asm @@ -13,9 +13,8 @@ //------------------------------------------------------------------------------ - EXPORT __aeabi_memmove - AREA Memmove, CODE, READONLY + INCLUDE AsmMacroExport.inc ; ;VOID @@ -26,7 +25,7 @@ ; IN UINT32 Size ; ); ; -__aeabi_memmove + RVCT_ASM_EXPORT __aeabi_memmove CMP r2, #0 BXEQ lr CMP r0, r1 diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memset.asm b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memset.asm index bae3c1f..0e67fad 100755 --- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memset.asm +++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memset.asm @@ -14,16 +14,13 @@ //------------------------------------------------------------------------------ - EXPORT __aeabi_memset - EXPORT __aeabi_memclr - EXPORT __aeabi_memclr4 - AREA Memset, CODE, READONLY + INCLUDE AsmMacroExport.inc ; void __aeabi_memclr4(void *dest, size_t n); ; void __aeabi_memclr(void *dest, size_t n); -__aeabi_memclr -__aeabi_memclr4 + RVCT_ASM_EXPORT __aeabi_memclr + RVCT_ASM_EXPORT __aeabi_memclr4 mov r2, #0 ; @@ -35,7 +32,7 @@ __aeabi_memclr4 ; IN UINT32 Character ; ); ; -__aeabi_memset + RVCT_ASM_EXPORT __aeabi_memset cmp r1, #0 bxeq lr ; args = 0, pretend = 0, frame = 0 diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/mullu.asm b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/mullu.asm index 3451c2c..d9979d0 100644 --- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/mullu.asm +++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/mullu.asm @@ -13,10 +13,8 @@ //------------------------------------------------------------------------------ - EXPORT __ARM_ll_mullu - EXPORT __aeabi_lmul - AREA Math, CODE, READONLY + INCLUDE AsmMacroExport.inc ; ;INT64 @@ -26,7 +24,7 @@ ; IN INT32 Multiplier ; ); ; -__ARM_ll_mullu + RVCT_ASM_EXPORT __ARM_ll_mullu mov r3, #0 // Make upper part of INT64 Multiplier 0 and use __aeabi_lmul @@ -38,7 +36,7 @@ __ARM_ll_mullu ; IN INT64 Multiplier ; ); ; -__aeabi_lmul + RVCT_ASM_EXPORT __aeabi_lmul stmdb sp!, {lr} mov lr, r0 umull r0, ip, r2, lr diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/switch.asm b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/switch.asm index e09c90c..f23aa42 100644 --- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/switch.asm +++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/switch.asm @@ -14,11 +14,10 @@ - EXPORT __ARM_switch8 - AREA ArmSwitch, CODE, READONLY + INCLUDE AsmMacroExport.inc -__ARM_switch8 + RVCT_ASM_EXPORT __ARM_switch8 LDRB r12,[lr,#-1] CMP r3,r12 LDRBCC r3,[lr,r3] diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uldiv.asm b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uldiv.asm index aed649b..6b6184e 100644 --- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uldiv.asm +++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uldiv.asm @@ -14,9 +14,8 @@ - EXPORT __aeabi_uldivmod - AREA Uldivmod, CODE, READONLY + INCLUDE AsmMacroExport.inc ; ;UINT64 @@ -26,7 +25,7 @@ ; IN UINT64 Divisor ; ) ; -__aeabi_uldivmod + RVCT_ASM_EXPORT __aeabi_uldivmod stmdb sp!, {r4, r5, r6, lr} mov r4, r1 mov r5, r0 diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uread.asm b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uread.asm index 3d58965..f369e4d 100644 --- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uread.asm +++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uread.asm @@ -14,10 +14,8 @@ - EXPORT __aeabi_uread4 - EXPORT __aeabi_uread8 - AREA Uread4, CODE, READONLY + INCLUDE AsmMacroExport.inc ; ;UINT32 @@ -26,7 +24,7 @@ ; IN VOID *Pointer ; ); ; -__aeabi_uread4 + RVCT_ASM_EXPORT __aeabi_uread4 ldrb r1, [r0] ldrb r2, [r0, #1] ldrb r3, [r0, #2] @@ -43,7 +41,7 @@ __aeabi_uread4 ; IN VOID *Pointer ; ); ; -__aeabi_uread8 + RVCT_ASM_EXPORT __aeabi_uread8 mov r3, r0 ldrb r1, [r3] diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uwrite.asm b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uwrite.asm index 85e1ba8..434a652 100644 --- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uwrite.asm +++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uwrite.asm @@ -13,10 +13,8 @@ //------------------------------------------------------------------------------ - EXPORT __aeabi_uwrite4 - EXPORT __aeabi_uwrite8 - AREA Uwrite4, CODE, READONLY + INCLUDE AsmMacroExport.inc ; ;UINT32 @@ -27,7 +25,7 @@ ; ); ; ; -__aeabi_uwrite4 + RVCT_ASM_EXPORT __aeabi_uwrite4 mov r2, r0, lsr #8 strb r0, [r1] strb r2, [r1, #1] @@ -46,7 +44,7 @@ __aeabi_uwrite4 ; ); ; ; -__aeabi_uwrite8 + RVCT_ASM_EXPORT __aeabi_uwrite8 mov r3, r0, lsr #8 strb r0, [r2] strb r3, [r2, #1] diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf b/ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf index 3487787..103f515 100644 --- a/ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf +++ b/ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf @@ -102,6 +102,7 @@ [Packages] MdePkg/MdePkg.dec + ArmPkg/ArmPkg.dec [LibraryClasses] -- 1.9.5.msysgit.0 _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
