There might be page table set SMM data region be XD. So we have to enable XD before enable paging. Or #PF might be generated.
mXdSupported is moved from C to ASM, because protected mode code can not refer global variable in long mode ASM. MSR_EFER/MSR_EFER_XD macro is moved from H to ASM as well. Unused ActivateXd() function is totally removed. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <[email protected]> Cc: "Fan, Jeff" <[email protected]> Cc: "Kinney, Michael D" <[email protected]> --- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S | 16 ++++++++++++++++ UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm | 16 ++++++++++++++++ UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 7 ------- UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 24 ------------------------ UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h | 15 ++++++--------- UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h | 3 --- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S | 20 ++++++++++++++++++-- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm | 19 +++++++++++++++++-- 8 files changed, 73 insertions(+), 47 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S index ec5b9a0..9587496 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S @@ -24,9 +24,13 @@ ASM_GLOBAL ASM_PFX(gcSmiHandlerSize) ASM_GLOBAL ASM_PFX(gSmiCr3) ASM_GLOBAL ASM_PFX(gSmiStack) ASM_GLOBAL ASM_PFX(gSmbase) +ASM_GLOBAL ASM_PFX(mXdSupported) ASM_GLOBAL ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard)) ASM_GLOBAL ASM_PFX(gSmiHandlerIdtr) +.equ MSR_EFER, 0xc0000080 +.equ MSR_EFER_XD, 0x800 + .equ DSC_OFFSET, 0xfb00 .equ DSC_GDTPTR, 0x30 .equ DSC_GDTSIZ, 0x38 @@ -122,6 +126,18 @@ L11: orl $BIT10, %eax L12: # as cr4.PGE is not set here, refresh cr3 movl %eax, %cr4 # in PreModifyMtrrs() to flush TLB. + +# enable NXE if supported + .byte 0xb0 # mov al, imm8 +ASM_PFX(mXdSupported): .space 1 + cmpb $0, %al + jz L13 + movl $MSR_EFER, %ecx + rdmsr + orw $MSR_EFER_XD,%ax # enable NXE + wrmsr +L13: + movl %cr0, %ebx orl $0x080010000, %ebx # enable paging + WP movl %ebx, %cr0 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm index ac1a9b4..5a112e1 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm @@ -22,6 +22,9 @@ .model flat,C .xmm +MSR_EFER EQU 0c0000080h +MSR_EFER_XD EQU 0800h + DSC_OFFSET EQU 0fb00h DSC_GDTPTR EQU 30h DSC_GDTSIZ EQU 38h @@ -43,6 +46,7 @@ EXTERNDEF gcSmiHandlerSize:WORD EXTERNDEF gSmiCr3:DWORD EXTERNDEF gSmiStack:DWORD EXTERNDEF gSmbase:DWORD +EXTERNDEF mXdSupported:BYTE EXTERNDEF FeaturePcdGet (PcdCpuSmmStackGuard):BYTE EXTERNDEF gSmiHandlerIdtr:FWORD @@ -128,6 +132,18 @@ gSmiCr3 DD ? or eax, BIT10 @@: ; as cr4.PGE is not set here, refresh cr3 mov cr4, eax ; in PreModifyMtrrs() to flush TLB. + +; enable NXE if supported + DB 0b0h ; mov al, imm8 +mXdSupported DB 0 + cmp al, 0 + jz @f + mov ecx, MSR_EFER + rdmsr + or ax, MSR_EFER_XD ; enable NXE + wrmsr +@@: + mov ebx, cr0 or ebx, 080010000h ; enable paging + WP mov cr0, ebx diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c index 99d03c4..41f57c0 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -1075,13 +1075,6 @@ SmiRendezvous ( InitializeSpinLock (&mSmmMpSyncData->CpuData[CpuIndex].Busy); } - // - // Try to enable NX - // - if (mXdSupported) { - ActivateXd (); - } - if (FeaturePcdGet (PcdCpuSmmProfileEnable)) { ActivateSmmProfile (CpuIndex); } diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c index ec4ec9b..f65ae87 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c @@ -30,11 +30,6 @@ UINTN mSmmProfileSize; UINTN mMsrDsAreaSize = SMM_PROFILE_DTS_SIZE; // -// The flag indicates if execute-disable is supported by processor. -// -BOOLEAN mXdSupported = FALSE; - -// // The flag indicates if execute-disable is enabled on processor. // BOOLEAN mXdEnabled = FALSE; @@ -1020,25 +1015,6 @@ CheckProcessorFeature ( } /** - Enable XD feature. - -**/ -VOID -ActivateXd ( - VOID - ) -{ - UINT64 MsrRegisters; - - MsrRegisters = AsmReadMsr64 (MSR_EFER); - if ((MsrRegisters & MSR_EFER_XD) != 0) { - return ; - } - MsrRegisters |= MSR_EFER_XD; - AsmWriteMsr64 (MSR_EFER, MsrRegisters); -} - -/** Enable single step. **/ diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h index 4548467..532c7b3 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h @@ -102,15 +102,6 @@ CheckFeatureSupported ( ); /** - Enable XD feature. - -**/ -VOID -ActivateXd ( - VOID - ); - -/** Update page table according to protected memory ranges and the 4KB-page mapped memory ranges. **/ @@ -128,7 +119,13 @@ CheckProcessorFeature ( VOID ); +// +// The flag indicates if execute-disable is supported by processor. +// extern BOOLEAN mXdSupported; +// +// The flag indicates if execute-disable is enabled on processor. +// extern BOOLEAN mXdEnabled; #endif // _SMM_PROFILE_H_ diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h index de6eb0a..66e49ad 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h @@ -53,9 +53,6 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. // CPU generic definition // #define CPUID1_EDX_XD_SUPPORT 0x100000 -#define MSR_EFER 0xc0000080 -#define MSR_EFER_XD 0x800 - #define CPUID1_EDX_BTS_AVAILABLE 0x200000 #define DR6_SINGLE_STEP 0x4000 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S index 7e9ac58..6a94d0a 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S @@ -24,8 +24,12 @@ ASM_GLOBAL ASM_PFX(gcSmiHandlerSize) ASM_GLOBAL ASM_PFX(gSmiCr3) ASM_GLOBAL ASM_PFX(gSmiStack) ASM_GLOBAL ASM_PFX(gSmbase) +ASM_GLOBAL ASM_PFX(mXdSupported) ASM_GLOBAL ASM_PFX(gSmiHandlerIdtr) +.equ MSR_EFER, 0xc0000080 +.equ MSR_EFER_XD, 0x800 + # # Constants relating to PROCESSOR_SMM_DESCRIPTOR # @@ -139,9 +143,21 @@ ASM_PFX(gSmiCr3): .space 4 call Base # push return address for retf later Base: addl $(LongMode - Base), (%rsp) # offset for far retf, seg is the 1st arg - movl $0xc0000080, %ecx + +# enable NXE if supported + .byte 0xb0 # mov al, imm8 +ASM_PFX(mXdSupported): .space 1 + cmpb $0, %al + jz NxeDone + movl $MSR_EFER, %ecx + rdmsr + orw $MSR_EFER_XD,%ax # enable NXE + wrmsr +NxeDone: + + movl $MSR_EFER, %ecx rdmsr - orb $1,%ah + orb $1,%ah # enable LME wrmsr movq %cr0, %rbx orl $0x080010000, %ebx # enable paging + WP diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm index 094cf2c..1d8fc34 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm @@ -29,8 +29,11 @@ EXTERNDEF gcSmiHandlerSize:WORD EXTERNDEF gSmiCr3:DWORD EXTERNDEF gSmiStack:DWORD EXTERNDEF gSmbase:DWORD +EXTERNDEF mXdSupported:BYTE EXTERNDEF gSmiHandlerIdtr:FWORD +MSR_EFER EQU 0c0000080h +MSR_EFER_XD EQU 0800h ; ; Constants relating to PROCESSOR_SMM_DESCRIPTOR @@ -135,9 +138,21 @@ gSmiCr3 DD ? call Base ; push return address for retf later Base: add dword ptr [rsp], @LongMode - Base; offset for far retf, seg is the 1st arg - mov ecx, 0c0000080h + +; enable NXE if supported + DB 0b0h ; mov al, imm8 +mXdSupported DB 0 + cmp al, 0 + jz @f + mov ecx, MSR_EFER + rdmsr + or ax, MSR_EFER_XD ; enable NXE + wrmsr +@@: + + mov ecx, MSR_EFER rdmsr - or ah, 1 + or ah, 1 ; enable LME wrmsr mov rbx, cr0 or ebx, 080010000h ; enable paging + WP -- 1.9.5.msysgit.0 _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
